ADC HighSpeed SAR - High-Speed SAR ADC Block

PIC32 MK dsPIC33C CH/CK

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High-speed SAR ADC with dedicated cores for simultaneous multi-channel acquisition. Ideal for motor control and high-throughput applications.

Block Inputs/Outputs

Inputs: None (hardware trigger or manual conversion)

Outputs: Dynamic based on enabled ADC cores

Dynamic Output Configuration

The block automatically creates output ports based on enabled ADC cores:

• Dedicated cores: One output per enabled ADC (ADC0_out, ADC1_out, etc.)
• Shared ADC7: One output per selected analog input
• Data type: Configurable (typically uint16)
• Output format: Raw ADC counts (right-aligned)

Example Output Configuration:

• ADC0 enabled → Output: ADC0_out (AN0 / PA0)
• ADC1 enabled → Output: ADC1_out (AN1 / PA1)
• ADC2 enabled → Output: ADC2_out (AN2 / PA2)
• ADC7 with AN10, AN15 selected → Outputs: AN10_out, AN15_out
• Total: 5 output ports

Block Output Datatype

The block outputs uint16 raw values directly from ADC data registers.

Scaling formula: Voltage = ADC_counts × (VREF / ADC_max)

Where ADC_max depends on resolution setting (4095 for 12-bit, 1023 for 10-bit, etc.).

Device Family Support Matrix

Key Features

Resolution 6/8/10/12-bit selectable per core Dedicated Cores 3-6 dedicated ADC cores (chip dependent) Shared ADC7 Software-configurable multiplexed core Speed Up to 3.25 Msps per core Triggers Independent triggers per core Special Inputs VBat, IVref, Temperature, CTMU

ADC Architecture

Dedicated ADC Cores (ADC0-ADC6)

• Hard-wired inputs: Each dedicated core has a fixed analog input pin
• Independent operation: Each core can sample simultaneously with different triggers
• No multiplexing: Zero channel switching delay
• Ideal for: Multi-phase motor current sensing, multi-channel synchronous acquisition

Shared ADC7

• Flexible input selection: Can be connected to any available ANx input
• Software-controlled multiplexing: Select input channel via mask parameters
• Excluded inputs: Cannot use same inputs as dedicated cores (AN0-AN6 typically reserved)
• Ideal for: Auxiliary measurements, voltage monitoring, additional channels

Configuration Parameters

Dedicated Core Settings (ADC0-ADC6)

Shared ADC7 Configuration

Special Input Channels

Timing Configuration

Trigger Sources

Available Trigger Types

Independent Triggering Example:

• ADC0 triggered by PWM1 Special Event (phase current U)
• ADC1 triggered by PWM1 Special Event (phase current V)
• ADC2 triggered by PWM2 Special Event (phase current W)
• ADC7 triggered by Timer3 Compare (DC bus voltage monitoring) All cores sample independently based on their respective triggers.

PWM-ADC Synchronization Strategies

Proper synchronization between PWM generation and ADC sampling is essential for motor control and power conversion. The High-Speed SAR ADC with dedicated cores provides exceptional flexibility for implementing optimal sampling strategies. Understanding when and how to trigger ADC conversions directly impacts control accuracy and system performance.

Synchronization Strategy Overview

The MCHP_ADC_HighSpeed_SAR block supports four fundamental synchronization strategies for different control requirements:

Strategy 1: Timer-Based Trigger (Independent Sampling)

ADC Configuration:

• Set ADCx_Trig = 'Timer3 Compare' (or any timer)
• Timer runs at fixed frequency independent of PWM
• Control task triggered by ADC interrupt or DMA completion

When to Use:

• General-purpose data acquisition
• Sensor monitoring at fixed sample rates
• Multi-rate control systems (different loops at different frequencies)
• Applications where PWM synchronization is not critical

Limitations:

• ❌ Not synchronized with PWM switching edges
• ❌ May sample during switching noise transients
• ❌ Not suitable for phase current sensing in motor control

Strategy 2: Timer → ADC → Task (Synchronized Acquisition)

ADC Configuration:

• Timer trigger starts ADC conversion
• ADC interrupt triggers control task execution
• Ensures fresh data before control algorithm runs

Key Benefit: Zero latency - control task always uses most recent ADC data (no stale samples).

Configuration Example:

% ADC Block Configuration:
ADC0_Enable = 'on';
ADC1_Enable = 'on';
ADC0_Trig = 'Timer3 Compare';  % Timer trigger
ADC1_Trig = 'Timer3 Compare';  % Same timer

% Timer3 Configuration:
Period = 1/10e3;  % 10 kHz sampling rate

% Scheduler Configuration:
% Set control task to trigger on ADC0 interrupt
% Task sample time = 'Inherited' (follows ADC trigger rate)

Best For:

• Feedback control systems requiring minimum latency
• Data logging applications
• Sensor monitoring with immediate processing

Strategy 3: PWM → ADC → Task (Motor Control Standard) ⭐ RECOMMENDED

⭐ This is the STANDARD approach for motor control and power conversion applications.

Key Benefits:

• ✅ Optimal sampling timing: Sample when PWM low-side FET is ON
• ✅ Noise immunity: Avoid switching transients
• ✅ Accurate current sensing: Sample during shunt current flow
• ✅ Automatic synchronization: Control rate matches PWM frequency
• ✅ Simultaneous sampling: Dedicated cores sample all phases at same instant

ADC Configuration Example (3-Phase FOC with Dedicated Cores):

% PWM Block Configuration (MCHP_PWM_HighSpeed or MCHP_MCPWM):
PWM_Mode = 'Center-aligned';
PWM_Frequency = 20e3;  % 20 kHz
SEVTCMP = 0;  % Trigger at PWM valley (center point)

% ADC Block Configuration (Dedicated Cores):
ADC0_Enable = 'on';  % Phase A current (AN0)
ADC1_Enable = 'on';  % Phase B current (AN1)
ADC2_Enable = 'on';  % Phase C current (AN2)

% All triggered by PWM valley for simultaneous sampling:
ADC0_Trig = 'PWM1 Special Event';
ADC1_Trig = 'PWM1 Special Event';
ADC2_Trig = 'PWM1 Special Event';

% All use 12-bit resolution:
ADC0_SELRES = '12-bit';
ADC1_SELRES = '12-bit';
ADC2_SELRES = '12-bit';

% Appropriate sample time for low-impedance shunt:
ADC0_SAMC = 10;  % TAD cycles
ADC1_SAMC = 10;
ADC2_SAMC = 10;

% Result: All 3 phase currents sampled simultaneously at PWM valley (20 kHz rate)
% Control task triggered by ADC0 interrupt completion

 Why Sample at PWM Valley? In center-aligned PWM for 3-phase motor control, the valley (center) is when all three low-side FETs are simultaneously ON. This is the only time when phase currents flow through shunt resistors, enabling accurate current measurement. The dedicated ADC cores allow true simultaneous sampling with zero multiplexing delay. Configuration Example with Shared ADC7 for Auxiliary Measurements:

% Dedicated cores for critical signals (simultaneous):
ADC0_Enable = 'on';  % Phase A current
ADC1_Enable = 'on';  % Phase B current
ADC2_Enable = 'on';  % Phase C current
ADC0_Trig = ADC1_Trig = ADC2_Trig = 'PWM1 Special Event';

% Shared ADC7 for slower auxiliary measurements:
ADC7_Enable = 'on';
ADC7_ANx = [AN10, AN15];  % DC bus voltage, temperature
ADC7_Trig = 'PWM1 Special Event';  % Same instant or slower rate

% Result: 3 phase currents + 2 auxiliary channels sampled at PWM valley

Trigger Source Mapping (Device-Specific):

Strategy 4: Multiple Triggers per PWM Period (Advanced Control)

Use Case: High-performance control requiring multiple measurements per PWM cycle.

Key Applications:

• Single-shunt FOC: Sample currents at multiple PWM sector transitions
• Dual sampling: Measure phase currents at peak and valley
• Sensorless FOC: Sample back-EMF at multiple rotor positions
• Digital power: Monitor voltage/current at different switching states

ADC Configuration Example (Single-Shunt FOC):

% PWM Block (MCHP_PWM_HighSpeed or MCHP_MCPWM):
PWM_Mode = 'Center-aligned';
TrigOut = [1 1 1];  % Enable 3 trigger outputs
TRIG1 = Period * 0.4;   % Before valley (sector 1)
SEVTCMP = 0;            % Valley (sector 2)
TRIG2 = Period * 0.6;   % After valley (sector 3)

% ADC Block Configuration (Dedicated cores for parallel sampling):
ADC0_Enable = 'on';  % Shunt current - Sector 1
ADC0_Trig = 'PWM1 TRIG1';

ADC1_Enable = 'on';  % Shunt current - Sector 2
ADC1_Trig = 'PWM1 Special Event';  % Valley

ADC2_Enable = 'on';  % Shunt current - Sector 3
ADC2_Trig = 'PWM1 TRIG2';

% All measure same shunt at different PWM sectors
% Reconstruct 3-phase currents from single shunt

Advantages:

• Maximum information extraction per PWM cycle
• Cost reduction (single shunt vs. 3 shunts)
• Improved state estimation for sensorless control
• Faster transient response

Considerations:

• ⚠️ Increased CPU load (multiple ADC interrupts per PWM cycle)
• ⚠️ Careful timing analysis required (ensure ADC completes before next trigger)
• ⚠️ Complex current reconstruction algorithms

Application-Specific Recommendations

Troubleshooting Synchronization Issues

Performance Optimization Tips

• Simultaneous Sampling: Assign critical signals (e.g., 3-phase currents) to dedicated cores ADC0-2 for true simultaneous acquisition
• Core Distribution: Balance channel assignment across available cores to maximize parallel conversion
• Resolution Selection: Use lowest resolution meeting accuracy requirements (10-bit often sufficient for motor control)
• SAMC Optimization: Calculate minimum SAMC based on source impedance: SAMC_min = 0.002 × R_source + 3
• DMA Integration: Enable DMA for ADC results to minimize CPU overhead in high-speed applications
• Interrupt Priority: Set ADC interrupt priority higher than control task for immediate data availability
• ADC7 Management: Use shared ADC7 for slower auxiliary measurements to avoid interfering with fast dedicated cores  Quick Start Recommendation: For 3-phase motor control applications, start with Strategy 3 (PWM → ADC → Task):
• Configure PWM with center-aligned mode and SEVTCMP = 0
• Assign phase currents to dedicated cores ADC0-2
• Set all ADC triggers to 'PWM1 Special Event'
• Use 12-bit resolution with SAMC=10 for shunt resistors
• Set control task to trigger on ADC0 interrupt

This configuration provides optimal current measurement with minimal setup complexity and leverages the dedicated core architecture for true simultaneous sampling.

Comparison with Other ADC Architectures

Related PWM Blocks for Synchronization

• MCHP_PWM_HighSpeed - High-speed PWM for dsPIC33C/CH/CK with multiple triggers
• MCHP_MCPWM - Motor Control PWM with advanced trigger capabilities
• MCHP_PWM - Standard PWM with special event trigger

Implementation Details

Key Registers Configured

Conversion Process

• Trigger received → Core enters sampling phase
• Sample for SAMC TADs → Acquire input voltage on S&H capacitor
• Hold and convert → SAR conversion (12/10/8/6 TAD depending on resolution)
• Result available → ADCDATAx register updated, interrupt/DMA triggered

Usage Examples

Example 1: 3-Phase Motor Current Sensing

Configuration:

• ADC0: Enabled, 12-bit, AN0 (Phase U current)
• ADC1: Enabled, 12-bit, AN1 (Phase V current)
• ADC2: Enabled, 12-bit, AN2 (Phase W current)
• ADC0/1/2 Trigger: PWM1 Special Event (valley sampling)
• ADC0/1/2 SAMC: 10 TAD (for <1kΩ source impedance) Result: Three phase currents sampled simultaneously at PWM valley, zero multiplexing delay, perfect for FOC algorithms.

Example 2: Multi-Channel Data Acquisition

Configuration:

• ADC0-ADC4: All enabled, 10-bit, dedicated inputs AN0-AN4
• ADC7: Enabled, scan mode with AN10, AN15, AN20
• ADC0-4 Trigger: Timer3 Compare (100kHz)
• ADC7 Trigger: Scan trigger (auto-sequenced) Result: 5 dedicated channels sampled at 100kHz + 3 scanned channels on ADC7 for auxiliary measurements.

Example 3: Battery Monitoring with Temperature Compensation

Configuration:

• Vbat: Enabled (battery voltage)
• IVTemp: Enabled (junction temperature)
• ADC7: Enabled, 12-bit, trigger: Timer2 (1kHz) Result: Periodic monitoring of battery voltage and chip temperature for thermal management.

Example 4: High-Impedance Sensor Interface

Configuration:

• ADC0: Enabled, 12-bit, AN0
• ADC_R: <50kΩ (high-impedance source)
• SAMC: Auto-calculated to 103 TAD
• Trigger: Manual (software controlled) Result: Accurate conversion from 50kΩ source with sufficient sampling time.

Performance Considerations

Conversion Speed vs Resolution

Multi-Core Throughput

• Parallel operation: All dedicated cores can convert simultaneously
• Aggregate throughput: Up to 6 cores × 1.6 Msps = 9.6 Msps total (PIC32MK)
• ADC7 scan mode: Adds sequential throughput for auxiliary channels

Troubleshooting

Common Issues

            Ensure chip has ADC7 shared core capability
            Check that desired ANx pins exist on selected chip
            Verify ANx not already used by dedicated cores

        
            Increase ADC_R impedance selection
            Verify SAMC auto-calculation meets minimum for source impedance
            Consider using buffer amplifier for sources >10kΩ

Device-Specific Notes

• PIC32MK: 6 dedicated cores (ADC0-5), full ADC7 scan capability, VBat/CTMU support
• dsPIC33C (WACP): 3 dedicated cores (ADC0-2), reduced ADC7 options, VBat/CTMU support
• dsPIC33C (Standard): 5 dedicated cores (ADC0-4), standard ADC7, no VBat/CTMU

Related Blocks

• ADC - Standard ADC for dsPIC30F/33F/33E
• ADC HighSpeed SAR dsPIC - Alternative HS SAR for dsPIC33C
• ADC HS 12b - 12-bit high-speed ADC for dsPIC33A
• PWM HS FEP - PWM with ADC trigger capability

See Also

ADC Blocks Overview | Block Reference | Motor Control Examples