ADC HighSpeed SAR dsPIC - High-Speed SAR ADC for dsPIC33C

dsPIC33C CH/CK

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MCHP_ADC_HighSpeed_SAR_dsPIC - dsPIC-style interface (this block) MCHP_ADC_HighSpeed_SAR - PIC32-style interface Both blocks configure the same hardware but with different parameter organization.

            MCHP_ADC_HighSpeed_SAR_dsPIC - dsPIC-style interface (this block)
            MCHP_ADC_HighSpeed_SAR - PIC32-style interface
        
        Both blocks configure the same hardware but with different parameter organization.

Supported Devices

• dsPIC33CH - Dual-core devices with master/slave architecture
• dsPIC33CK - Single-core high-performance DSCs

Key Features

• 3-6 dedicated ADC cores depending on device
• Shared ADC7 for auxiliary channels
• 6/8/10/12-bit resolution per core
• Up to 3.25 Msps per core
• PWM-synchronized acquisition
• DMA support

Configuration Parameters

dsPIC-style parameter interface with array-based configuration for dedicated cores.

Related Blocks

• ADC HighSpeed SAR - PIC32-style interface
• ADC - Standard ADC for dsPIC30F/33F/33E

See Also

ADC Blocks Overview