ADC HS 12b - 12-bit High-Speed ADC for dsPIC33A - MPLAB Device Blocks for Simulink

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Advanced 12-bit high-speed ADC with flexible software sequencing for dsPIC33A. Each ADC core supports 6 independent sequences with 6 conversions per sequence, enabling complex multi-channel acquisition strategies.

dsPIC33A Variant Support Matrix

Variant	Module Type	ADC Cores	Max Channels per Core	Example Device
Perseus (STX04)	DOS_03459_adc_pc_ctrl_upb_v2	2 (ADC1, ADC2)	20 each	33AK128MC106
Pegasus (STX32)	DOS_02976_adc_12b_upb_v2	5 (ADC1-5)	16 each	33AK512MPS512
Blue Ridge (STX33)	DOS_05972_adc_12b_upb_v3_itc	3 (ADC1-3)	12 each	33AK256MPS306
Serpens (STX21)	DOS_05972_adc_12b_upb_v3_adc	2 (ADC1, ADC2)	20, 39	33AKV512GM510

Quick Reference

Application	Recommended Strategy	Key Configuration
3-Phase FOC Motor Control	⭐ PWM → ADC → Task	`ADC1_seq0: AN0,AN1,AN2` `Trigger: 'PWM1 Special Event'` `SEVTCMP: 0` (PWM valley)
Single-Shunt FOC	Multiple Triggers/Period	`seq0-2: AN0` (shunt) `Triggers: TRIG1, SEVTCMP, TRIG2` 3 samples/PWM cycle
Dual Motor Control	Independent ADC cores	`ADC1: Motor1 (SCCP1 trigger)` `ADC2: Motor2 (SCCP5 trigger)` Parallel sampling
Multi-Channel DAQ	Timer → ADC → Task	`18 channels across seq0-2` `Trigger: SCCP1` Simultaneous acquisition
DC-DC Converter	PWM → ADC → Task	`seq0: Vout, Iout` `Trigger: PWM Special Event` Sample during FET ON

⭐ Most Common: Use PWM Special Event trigger at valley (SEVTCMP: 0) for center-aligned motor control PWM

Supported Device Families

dsPIC33A

Key Features

Resolution Fixed 12-bit high-precision Sequencing 6 sequences × 6 conversions per sequence Flexibility Any channel to any sequence slot Synchronization SCCP/SSC timer trigger integration Multiple Cores 2-5 independent ADC cores High Speed Optimized for FOC motor control

Software Sequencing Architecture

Sequence Configuration

6 Sequences: seq0 through seq5 for each ADC core
6 Conversions per sequence: Each sequence can perform up to 6 channel conversions
Dynamic assignment: Select any available ANx channel for any conversion slot
Independent triggers: Each sequence can have its own trigger source Sequence Example:
ADC1_seq0: AN0, AN1, AN2 (3-phase currents) - Trigger: PWM1 Special Event
ADC1_seq1: AN5, AN6 (DC bus voltage/current) - Trigger: PWM2 Special Event
ADC2_seq0: AN20, AN21 (auxiliary sensors) - Trigger: SCCP1 Timer

Configuration Parameters

ADC Core Selection

Parameter	Description	Options
ADC1_Enable - ADC5_Enable	Enable individual ADC cores	on / off (availability depends on chip variant)

Sequence Configuration (for each enabled ADC)

Parameter	Description	Details
ADCx_seq0	Channel for sequence 0, conversion 0	Dropdown with available ANx channels (e.g., “Not Used”, “AN0”, “AN1”, …)
ADCx_seq0_1 to ADCx_seq0_5	Additional conversions in sequence 0	Up to 6 conversions total per sequence
ADCx_seq1 through ADCx_seq5	Additional sequences with 6 conversions each	Complete flexibility in channel assignment

Trigger Configuration

Parameter	Description	Available Triggers
ADCx_seq0_Trig	Trigger source for sequence 0	• Manual (software)
ADCx_seq1_Trig - ADCx_seq5_Trig	Triggers for sequences 1-5

PWM-ADC Synchronization Strategies

Proper ADC trigger configuration is critical for motor control and power conversion. The dsPIC33A ADC supports multiple synchronization strategies, each optimized for different control requirements. Understanding when and how to trigger ADC conversions directly impacts control accuracy and performance.

Strategy Overview

The MCHP_ADC_HS_12b block supports four fundamental synchronization strategies:

Strategy 1: Timer-Based Trigger (Independent Sampling)

ADC Configuration:

Set ADCx_seq0_Trig = 'SCCP1' or 'SSC1'
Timer runs at fixed frequency independent of PWM
Control task triggered by ADC interrupt completion

When to Use:

General-purpose data acquisition
Sensor monitoring at fixed intervals
Multi-loop control with different sampling rates
Applications where PWM synchronization is not critical

Limitations:

❌ Not synchronized with PWM switching
❌ May sample during switching noise/transients
❌ Not suitable for phase current sensing in motor control

Strategy 2: Timer → ADC → Task (Synchronized Acquisition)

ADC Configuration:

Timer trigger starts ADC conversion
ADC interrupt triggers control task execution
Ensures fresh data before control algorithm runs

Key Benefit: Zero latency - control task always uses the most recent ADC data (no stale samples).

Configuration Example:

% ADC Block Configuration:
ADC1_Enable = 'on';
ADC1_seq0 = 'AN0';      % First channel
ADC1_seq0_1 = 'AN1';    % Second channel
ADC1_seq0_Trig = 'SCCP1';  % Timer trigger

% SCCP1 Timer Block:
Period = 1/10e3;  % 10 kHz sampling rate

% Scheduler Configuration:
% Set control task to be triggered by ADC1 interrupt
% Task sample time = 'Inherited' (follows ADC trigger rate)

Best For:

Feedback control systems requiring minimum latency
Data logging applications
Sensor monitoring with immediate processing

Strategy 3: PWM → ADC → Task (Motor Control Standard) ⭐ RECOMMENDED

⭐ This is the STANDARD approach for motor control and power conversion applications.

Key Benefits:

✅ Optimal sampling timing: Sample when PWM low-side FET is ON
✅ Noise immunity: Avoid switching transients
✅ Accurate current sensing: Sample during shunt current flow
✅ Automatic synchronization: Control rate matches PWM frequency

ADC Configuration Example (3-Phase FOC):

% PWM Block Configuration (MCHP_PWM_HS_FEP):
PWM_Mode = 'Center-aligned';
PWM_Frequency = 20e3;  % 20 kHz
SEVTCMP = 0;  % Trigger at PWM valley (center point)

% ADC Block Configuration:
ADC1_Enable = 'on';

% Phase current sensing (triggered by PWM valley):
ADC1_seq0 = 'AN0';      % Phase A current (Iu)
ADC1_seq0_1 = 'AN1';    % Phase B current (Iv)
ADC1_seq0_2 = 'AN2';    % Phase C current (Iw)
ADC1_seq0_Trig = 'PWM1 Special Event';  % PWM valley trigger

% DC bus voltage (same trigger):
ADC1_seq1 = 'AN5';      % DC bus voltage
ADC1_seq1_Trig = 'PWM1 Special Event';  % Same instant as currents

% Result: ADC samples all signals at PWM valley (20 kHz rate)
% Control task triggered by ADC1 interrupt completion

 Why Sample at PWM Valley? In center-aligned PWM for 3-phase motor control, the valley (center) is when all three low-side FETs are simultaneously ON. This is the only time when phase currents flow through shunt resistors, enabling accurate current measurement. Sampling at any other time results in incorrect or zero current readings. Trigger Sources for dsPIC33A:

PWM Block	Trigger Configuration	ADC Trigger Selection
MCHP_PWM_HS_FEP	Set	SEVTCMP
MCHP_MCPWM	Set	TRIG1/2/3

Strategy 4: Multiple Triggers per PWM Period (Advanced Control)

Use Case: High-performance control requiring multiple measurements per PWM cycle.

Key Applications:

Single-shunt FOC: Sample currents at multiple PWM sector transitions
Dual sampling: Measure phase currents at peak and valley
Sensorless FOC: Sample back-EMF at multiple rotor positions
Digital power: Monitor voltage/current at different switching states

ADC Configuration Example (Single-Shunt FOC):

% PWM Block (MCHP_PWM_HS_FEP):
PWM_Mode = 'Center-aligned';
TRIG1 = Period * 0.4;   % Before valley
SEVTCMP = 0;            % Valley
TRIG2 = Period * 0.6;   % After valley

% ADC Block Configuration:
ADC1_Enable = 'on';

% Sequence 0: First current sample (sector 1)
ADC1_seq0 = 'AN0';      % Shunt current
ADC1_seq0_Trig = 'PWM1 TRIG1';

% Sequence 1: Second current sample (sector 2)
ADC1_seq1 = 'AN0';      % Same shunt (different sector)
ADC1_seq1_Trig = 'PWM1 Special Event';  % Valley

% Sequence 2: Third current sample (sector 3)
ADC1_seq2 = 'AN0';      % Same shunt (different sector)
ADC1_seq2_Trig = 'PWM1 TRIG2';

% Result: 3 current measurements per PWM period
% Reconstruct 3-phase currents from single shunt

Advantages:

Maximum information extraction per PWM cycle
Improved state estimation (sensorless control)
Faster transient response
Cost reduction (single shunt vs. 3 shunts)

Considerations:

⚠️ Increased CPU load (multiple sequences to process)
⚠️ Careful timing analysis required (ensure ADC completes before next trigger)
⚠️ Complex reconstruction algorithms

Application-Specific Recommendations

Application	Recommended Strategy	ADC Configuration
3-Phase FOC Motor Control	PWM → ADC → Task (Strategy 3)	• seq0: 3 phase currents
Single-Shunt FOC	Multiple Triggers (Strategy 4)	• seq0-2: Shunt current at 3 sector transitions
BLDC Motor Control	PWM → ADC → Task (Strategy 3)	• seq0: DC bus current
PFC Boost Converter	PWM → ADC → Task (Strategy 3)	• seq0: Input current, output voltage
DC-DC Buck/Boost	PWM → ADC → Task (Strategy 3)	• seq0: Output voltage/current
Multi-Axis Motion Control	Multiple independent PWM→ADC chains	• ADC1: Motor 1 (PWM1 trigger)
General Data Acquisition	Timer → ADC → Task (Strategy 2)	• Multiple sequences at fixed rate

Troubleshooting Synchronization Issues

Problem	Likely Cause	ADC Configuration Fix
Phase currents read as zero	ADC not triggered at PWM valley	• Verify:
Noisy ADC readings	Sampling during switching transients	• Change trigger to PWM valley or after settling
No ADC trigger available in dropdown	PWM block not configured with triggers	• In PWM block: Enable
Control task not synchronized with ADC	Task triggered by timer, not ADC interrupt	• In Scheduler: Set task trigger to ADC interrupt
Missing ADC samples	ADC overrun (next trigger before conversion complete)	• Reduce number of conversions per sequence
Inconsistent trigger timing	Multiple sequences with overlapping triggers	• Verify ADC conversion time + margin between triggers

Performance Optimization Tips

Core Distribution: Distribute high-frequency channels across multiple ADC cores (ADC1-5) for parallel sampling
Sequence Organization: Group channels with same trigger into one sequence to minimize overhead
Conversion Time: Calculate total sequence conversion time: N_channels × (SAMC + 12 cycles). Ensure completion before next trigger.
DMA Usage: For high-speed applications, enable DMA to transfer ADC results without CPU intervention
Interrupt Priority: Set ADC interrupt priority higher than control task to ensure immediate data processing  Quick Start Recommendation: For most motor control applications, start with Strategy 3 (PWM → ADC → Task):
Configure PWM with center-aligned mode and SEVTCMP = 0
Set ADC sequence trigger to 'PWM1 Special Event'
Assign phase current channels to same sequence
Set control task to trigger on ADC interrupt This provides optimal current measurement with minimal configuration complexity.

MCHP_PWM_HS_FEP - High-resolution PWM for dsPIC33A with multiple triggers
MCHP_MCPWM - Motor Control PWM with advanced trigger capabilities
MCHP_PWM_HighSpeed - High-speed PWM for dsPIC33C

Device-Specific Capabilities

Perseus (33AK128MC106) - STX04

ADC Cores: 2 (ADC1, ADC2)
Channels: 20 per core (AN0-AN19)
Timers: SSC 1, 2, 3, 4, 9
Best for: Dual motor control, isolated converters

Pegasus (33AK512MPS512) - STX32

ADC Cores: 5 (ADC1-5)
Channels: 16 per core (AN0-AN15)
Timers: SCCP 1-9 (more trigger options)
Best for: Multi-axis motor control, multi-phase power

Blue Ridge (33AK256MPS306) - STX33

ADC Cores: 3 (ADC1-3)
Channels: 12 per core (AN0-AN11)
Timers: SSC 1, 2, 3, 4, 5
Best for: Cost-optimized motor control

Serpens (33AKV512GM510) - STX21

ADC Cores: 2 (ADC1, ADC2)
Channels: ADC1=20 (AN0-AN19), ADC2=39 (AN0-AN38)
Timers: SCC 1, 2, 3, 4, 9
Best for: High channel count applications

Block Output Datatype

The block supports 1 output datatype representation:

Output Type	Range	Description
uint16	0 to 4095	12-bit right-aligned raw ADC counts

Uint Raw Output (1 option)

Integer values transferred directly from ADC data registers—no runtime computation. Users handle conversion to physical units (voltage, current, temperature).

Scaling formula: Voltage = ADC_counts × (VREF / 4095)

Hardware Considerations: dsPIC33A devices have hardware FPU—float scaling is processed efficiently.

Dynamic Output Generation

The block creates output ports automatically based on sequence configuration:

Output per conversion: Each assigned channel in each sequence creates one output
Port naming: ADCx_seqY_Z format (e.g., ADC1_seq0_0, ADC1_seq0_1, ADC2_seq1_0)
Data type: uint16 (12-bit right-aligned)
Trigger-based updates: Each output updates when its sequence trigger fires Output Example:ADC1: seq0 → AN0, AN1, AN2 | seq1 → AN5ADC2: seq0 → AN10, AN11Outputs:
ADC1_seq0_0 (AN0)
ADC1_seq0_1 (AN1)
ADC1_seq0_2 (AN2)
ADC1_seq1_0 (AN5)
ADC2_seq0_0 (AN10)
ADC2_seq0_1 (AN11) Total: 6 outputs

Usage Examples

Example 1: 3-Phase FOC Motor Control

Configuration:

ADC1 seq0: AN0 (Iu), AN1 (Iv), AN2 (Iw) - Trigger: PWM1 Special Event
ADC1 seq1: AN5 (Vdc) - Trigger: PWM1 Special Event (same instant)
ADC2 seq0: AN10 (Temperature) - Trigger: SSC3 (lower frequency) Result: 3-phase currents + DC bus sampled synchronously with PWM, temperature sampled periodically.

Example 2: Dual Motor Control (Pegasus)

Motor 1 (ADC1):

seq0: AN0, AN1, AN2 (currents) - Trigger: SCCP1
seq1: AN5 (position feedback) - Trigger: SCCP2 Motor 2 (ADC2):
seq0: AN8, AN9, AN10 (currents) - Trigger: SCCP5
seq1: AN12 (position feedback) - Trigger: SCCP6 Result: Independent control of two motors with isolated ADC resources.

Example 3: Multi-Channel Data Acquisition