MCHP PGA Documentation

dsPIC33C CH/CK

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Digitally-controlled gain amplifier with calibration for precision analog signal conditioning

Block Overview

The MCHP_PGA block provides access to the Programmable Gain Amplifier (PGA) peripheral available in select dsPIC33C, dsPIC33CH, and dsPIC33CK devices. The PGA offers digitally-controlled gain settings with calibration capabilities, enabling precision signal conditioning for sensor inputs and ADC front-end applications.

                Software-configurable gain: 1×, 2×, 4×, 8×, 16×, 32× (device-dependent)
                Runtime gain adjustment via block input or register write
                Offset and gain calibration registers for precision measurements
                Direct connection to DACOUT pins or internal ADC inputs
                Single-ended or differential input modes
                Eliminates external amplifier circuits and reduces BOM cost

Supported Device Families

Output Routing: PGA outputs can be routed to DACOUT pins (for external ADC or monitoring) or kept internal (for direct connection to on-chip ADC). The block automatically configures pin assignments based on your selection.

Operating Modes

1. Single-Ended Input Mode

Configuration:

• Positive Input (PGAxP): Signal source connected to PGAxP pin
• Negative Input (PGAxN): Grounded (single-ended reference)
• Gain: Digitally selectable (2⁰ = 1×, 2¹ = 2×, 2² = 4×, up to 2⁵ = 32×)
• Output: V_OUT = Gain × (V_PGAxP - GND)
• Use Case: Single-ended sensor signals, voltage measurement

2. Differential Input Mode

Configuration:

• Positive Input (PGAxP): Differential signal high side
• Negative Input (PGAxN): Differential signal low side
• Gain: Applied to differential voltage
• Output: V_OUT = Gain × (V_PGAxP - V_PGAxN)
• Use Case: Differential sensor signals, common-mode noise rejection

3. Cascaded Gain Stages

Configuration:

• PGA1: First stage amplification (e.g., 4×)
• PGA2: Second stage amplification (e.g., 8×)
• Total Gain: 4× × 8× = 32× (beyond single PGA range)
• Connection: PGA1_OUT → PGA2_IN (internal or external)
• Use Case: Very low-level signals requiring high gain

Block Parameters

Register Configuration

PGAxCON Register (x = 1 or 2)

// PGA Control Register PGAxCON = (PGAEN « 15) | // PGA Enable (1 = enabled) (PGOEN « 14) | // Output Enable (1 = connect to DACOUTx) (SELPI « 11) | // Positive Input Select [2:0] (SELNI « 8) | // Negative Input Select [2:0] (GAIN « 0); // Gain Select [2:0] (0=1×, 1=2×, 2=4×, 3=8×, 4=16×, 5=32×) // Example: PGA1 with 8× gain, differential input, output enabled PGA1CON = 0x8B18; // 1000_1011_0001_1000 // Bit 15 (PGAEN) = 1 → PGA enabled // Bit 14 (PGOEN) = 0 → Output to DACOUT1 // Bits 13:11 (SELPI) = 001 → Positive input PGA1P1 // Bits 10:8 (SELNI) = 011 → Negative input PGA1N3 // Bits 2:0 (GAIN) = 011 → Gain = 2³ = 8×

Runtime Gain Update

Pin Configuration

Application Examples

Example 1: Sensor Signal Conditioning with Fixed Gain

Application: Temperature sensor with 0-100mV output // Configuration: // - PGA1Gain = “Gain 16 (2⁴)” // - PGA1P_pin = “PGA1P1 / RA0 / Pin[2]” (sensor output) // - PGA1N_pin = “Ground (Single-Ended mode)” // - PGA1Output = “off” (internal to ADC) // - PGA1Gain_BlockInput = “off” (fixed gain) // Hardware connections: // - Temperature sensor output (0-100mV) → PGA1P1 (RA0) // - PGA1 output (internal) → ADC_CH1 // Register configuration: PGA1CONbits.PGAEN = 1; // Enable PGA1 PGA1CONbits.PGOEN = 0; // Internal output only PGA1CONbits.SELPI = 1; // PGA1P1 selected PGA1CONbits.SELNI = 0; // Grounded (single-ended) PGA1CONbits.GAIN = 4; // 2⁴ = 16× gain // Signal chain: // Sensor: 0-100mV → PGA (16×) → 0-1.6V → ADC → Digital value // Full sensor range maps to 0-1.6V ADC input (within 0-3.3V range)

Example 2: Dynamic Gain Control for Wide Input Range

Example 3: Differential Current Sensing for Motor Control

Application: Motor current measurement via shunt resistor // Configuration: // - PGA1Gain = “Gain 32 (2⁵)” (maximum amplification) // - PGA1P_pin = “PGA1P1 / RA0 / Pin[2]” (shunt high side) // - PGA1N_pin = “PGA1N1 / RA1 / Pin[3]” (shunt low side) // - PGA1Output = “off” (internal to ADC) // - PGA1Gain_BlockInput = “off” // Hardware: // - Motor → 0.01Ω shunt → Motor_GND // - Shunt voltage: 10A × 0.01Ω = 100mV (differential) // - PGA1P (high side) and PGA1N (low side) measure shunt voltage // Register configuration: PGA1CONbits.PGAEN = 1; // Enable PGA1 PGA1CONbits.PGOEN = 0; // Internal output PGA1CONbits.SELPI = 1; // PGA1P1 (shunt high) PGA1CONbits.SELNI = 1; // PGA1N1 (shunt low) PGA1CONbits.GAIN = 5; // 2⁵ = 32× gain // Current measurement: // Motor current: 10A → Shunt: 100mV → PGA: 3.2V → ADC // ADC reading × (3.3V/4096) / 32 / 0.01Ω = Motor current // Synchronization with PWM: // - Trigger ADC from PWM event // - Sample during PWM off-time for clean measurement // - Provides real-time current feedback for FOC algorithm

Example 4: Cascaded PGA for Ultra-High Gain

Application: Piezoelectric sensor with μV output // Configuration: // - PGA1: Gain 32× (first stage) // - PGA2: Gain 32× (second stage) // - Total gain: 32 × 32 = 1024× // PGA1 Configuration: // - PGA1Gain = “Gain 32 (2⁵)” // - PGA1P_pin = “PGA1P1 / RA0” (piezo sensor) // - PGA1N_pin = “Ground (Single-Ended mode)” // - PGA1Output = “on” → DACOUT1 (external connection to PGA2) // PGA2 Configuration: // - PGA2Gain = “Gain 32 (2⁵)” // - PGA2P_pin = “PGA2P1 / RB0” (connected to DACOUT1) // - PGA2N_pin = “Ground (Single-Ended mode)” // - PGA2Output = “off” (internal to ADC) // External connection: // DACOUT1 (PGA1 output) → PGA2P1 (wire or PCB trace) // Signal chain: // Piezo: 3mV → PGA1 (32×) → 96mV → PGA2 (32×) → 3.072V → ADC // Total gain: 1024× (60dB) // Note: Watch for noise pickup on DACOUT1 → PGA2P1 connection // Use short trace, ground plane, and decoupling capacitor

Calibration and Offset Correction

PGA Offset Error Sources

• Input Offset Voltage: Inherent op-amp offset (typically ±1-5 mV)
• Gain Error: Deviation from ideal gain (typically ±1-3%)
• Temperature Drift: Offset changes over temperature (μV/°C)
• Reference Errors: Ground reference or supply voltage variations

Software Calibration Procedure

// Two-point calibration for PGA accuracy // Step 1: Zero-point calibration (offset correction) // Apply 0V to both PGA inputs (short P and N to ground) ADC_offset = ADC_Read(); // Measure output with 0V input // Store offset for subtraction during measurement // Step 2: Full-scale calibration (gain correction) // Apply known reference voltage (e.g., 1.000V from precision source) ADC_fullscale = ADC_Read(); // Measure output with known input gain_error = (ADC_fullscale - ADC_offset) / Expected_Value; // Store gain error for multiplication correction // Step 3: Apply calibration to measurements ADC_raw = ADC_Read(); ADC_calibrated = (ADC_raw - ADC_offset) / gain_error; Voltage_actual = ADC_calibrated × (Vref / 4096) / PGA_Gain;

Automatic Gain Ranging with Calibration

                Perform calibration at operating temperature for best accuracy
                Store calibration data in EEPROM or Flash for persistence across power cycles
                Re-calibrate periodically if drift is significant (e.g., every hour or temperature change)
                Use high-precision reference voltage source for gain calibration (better than 0.1% accuracy)

Design Guidelines

Input Signal Conditioning

• Input Range: Ensure input signal stays within 0 to VDD range (typically 0-3.3V)
• Over-voltage Protection: Add clamping diodes for signals that may exceed VDD
• Input Filtering: Use RC filter (e.g., 1kΩ + 100nF) to reduce high-frequency noise
• ESD Protection: Include series resistor (1-10kΩ) for ESD-sensitive inputs

Gain Selection Strategy

Gain Selection Guidelines:

• Fixed Gain: Use when signal amplitude is well-known and constant
• Dynamic Gain: Use for signals with wide dynamic range (>100:1)
• Optimal Range: Target ADC input of 0.5-2.5V for best SNR and linearity
• Headroom: Leave 10-20% margin to avoid saturation on signal peaks
• Noise Floor: Higher gain amplifies noise; balance gain vs. noise requirements

Output Routing Considerations

PCB Layout Best Practices

• Separate Grounds: Use analog ground plane, connect to digital ground at single point
• Short Traces: Keep PGA input traces as short as possible (<1 inch preferred)
• Guard Rings: Surround sensitive input traces with grounded guard traces
• Decoupling: Place 100nF capacitor close to VDD pin (<5mm)
• Shielding: Route PGA signals away from switching noise sources (PWM, clocks)

Troubleshooting

Related Blocks

• [MCHP_OP_AMP] - Operational amplifier for custom gain circuits
• [MCHP_HighSpeed_AnalogComparator] - Threshold detection after amplification
• [MCHP_ADC_HS_SAR_dsPIC33] - High-speed ADC for digitizing PGA outputs
• [MCHP_ADC_CoreIndependent_PIC32C] - SAM family ADC integration [← Back to Analog Blocks]