MCHP DAC SAMx Documentation

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High-performance DAC for waveform generation and precision voltage output

Block Overview

The MCHP_DACC_SAMx block provides access to the Digital-to-Analog Converter Controller (DACC) available in SAM E5x, SAM E7x, and SAM C2x microcontrollers. This peripheral enables high-quality analog voltage generation for applications including waveform synthesis, precision voltage references, audio output, and control signal generation.

                10-bit or 12-bit resolution (device-dependent)
                Dual-channel independent or differential output modes
                Up to 1 MSPS conversion rate
                Internal or external voltage reference options
                Built-in waveform generation capabilities
                DMA support for continuous waveform streaming
                Low glitch energy and monotonic output

Supported Device Families

Output Modes: The DACC supports both single-ended outputs (DAC0 and DAC1 independent) and differential output mode (DAC0 - DAC1), providing flexibility for various signal generation requirements.

Operating Modes

1. Single-Ended Output Mode

Configuration: Independent DAC channels

• DAC0 Output: 0 to VREF voltage range on DAC0 pin
• DAC1 Output: 0 to VREF voltage range on DAC1 pin
• Resolution: 10-bit (0-1023) or 12-bit (0-4095)
• Update: Independent data registers for each channel
• Use Case: Dual independent voltage sources, stereo audio, multi-channel control

2. Differential Output Mode

Configuration: Differential voltage output

• Output: V_OUT = DAC0 - DAC1 (differential voltage)
• Range: -VREF to +VREF (doubled output range)
• Common Mode: Typically VREF/2 for maximum swing
• Advantage: Noise cancellation, doubled voltage swing
• Use Case: Differential signaling, balanced audio, precision offset generation

3. Waveform Generation Mode

Configuration: Automatic waveform synthesis

• Sine Wave: Pure sine generation using internal sine table
• Triangle Wave: Linear ramp up/down waveform
• Sawtooth Wave: Ramp waveform (up or down)
• DMA-based: Arbitrary waveforms from memory buffer
• Use Case: Function generator, audio synthesis, test signal generation

Block Parameters

Block Input Datatype

The block supports 2 input datatype representations:

⚠️ Important: The block performs no range checking on inputs. Users must clamp values before the block input (e.g., using a Saturation block) to prevent overflow, regardless of datatype.

Float Input (1 option)

Normalized control—the block handles scaling internally. Use range [0, 1] for single-ended mode or [-1, 1] for differential mode.

Hardware Considerations: SAM devices (Cortex-M4F) have single-precision FPU—float inputs are processed efficiently.

Integer Input (1 option)

Values written directly to DAC registers—no runtime computation. Valid range: 0–4095 (12-bit: E5x/E7x) or 0–1023 (10-bit: C2x). Users handle scaling:

Scaling formula: DAC_count = (Voltage / VREF) × Max_Count

Register Configuration

DACC Control Register (DACC_CR)

// DAC Control Register DACC_CR = (SWRST « 0); // Software reset (write 1 to reset) // DAC Mode Register (DACC_MR) DACC_MR = (DIFF « 23) | // Differential mode (0=single, 1=diff) (PRESCALER « 8) | // Prescaler for DAC clock (STARTUP « 24) | // Startup time selection (MAXS « 0) | // Max speed mode (WORD « 4) | // Transfer mode (0=half-word, 1=word) (REFRESH « 8); // Refresh period for output

Single-Ended Mode Configuration

// Enable DAC channels independently DACC_CHER = (1 « 0) | // Enable DAC0 (1 « 1); // Enable DAC1 // Set initial output values DACC_CDR0 = 2048; // DAC0 initial (mid-scale for 12-bit) DACC_CDR1 = 2048; // DAC1 initial (mid-scale) // Runtime updates DACC_CDR0 = new_value_dac0; // Update DAC0 output DACC_CDR1 = new_value_dac1; // Update DAC1 output // Voltage calculation: // V_DAC0 = (DACC_CDR0 / 4095) × VREF (for 12-bit) // V_DAC1 = (DACC_CDR1 / 4095) × VREF

Differential Mode Configuration

// Enable differential mode DACC_MRbits.DIFF = 1; // Enable both DAC channels (required for differential) DACC_CHER = 0x03; // Enable DAC0 and DAC1 // Set differential output // For centered bipolar output (±VREF/2): int16_t diff_value = 0; // 0 = center (0V differential) // Convert signed value to DAC codes: uint16_t dac0_code = 2048 + (diff_value / 2); // Positive side uint16_t dac1_code = 2048 - (diff_value / 2); // Negative side DACC_CDR0 = dac0_code; DACC_CDR1 = dac1_code; // Differential voltage: // V_DIFF = V_DAC0 - V_DAC1 // = [(dac0_code - dac1_code) / 4095] × VREF // = (diff_value / 4095) × VREF

Pin Configuration (Automatic)

Application Examples

Example 1: DC Voltage Reference Generation

Application: Precision 1.65V reference for ADC bias // Configuration: // - DIFF = “Single-Ended Outputs” // - DAC0_OUTPUT_PIN = “DAC0 / PB13 / Pin[57]” (enabled) // - DAC0_INITIAL_OUTPUT = 2048 (mid-scale for 12-bit) // - DAC0_INPUT = “off” (static reference) // - DAC1_OUTPUT_PIN = “Not used” // - VREF = 3.3V (internal or external) // Initial configuration: DACC_MRbits.DIFF = 0; // Single-ended mode DACC_CHER = 0x01; // Enable DAC0 only DACC_CDR0 = 2048; // 2048/4095 × 3.3V = 1.65V // Result: // DAC0 pin outputs stable 1.65V for ADC single-ended biasing // No code execution needed after initialization // Low drift, low noise reference voltage

Example 2: Sine Wave Audio Generation

Example 3: Differential Motor Control Signal

Application: Balanced command voltage for motor driver // Configuration: // - DIFF = “Differential Outputs” // - DAC0_FORCED_OUTPUT_PIN = “DAC0 / PB13 / Pin[57]” // - DAC1_FORCED_OUTPUT_PIN = “DAC1 / PD0 / Pin[89]” // - DACC_DIFF_INITIAL_OUTPUT = 0 (0V differential) // - DAC_INPUT_DIFF = “on” (runtime control) // - DAC_INPUT_DIFF_SAT = “on” (prevent overflow) // Motor speed command: -100% to +100% // Convert to differential DAC value: float motor_command = 0.75; // 75% forward // Map -1.0 to +1.0 → -2048 to +2048 (12-bit centered) int16_t diff_value = (int16_t)(motor_command * 2048.0); // Block input receives diff_value // Block automatically converts to DAC0/DAC1 codes: uint16_t dac0 = 2048 + diff_value/2; // High side uint16_t dac1 = 2048 - diff_value/2; // Low side // Differential output: // V_DIFF = (diff_value / 2048) × (VREF/2) // For 75% command: V_DIFF = 0.75 × 1.65V = 1.24V // Motor driver receives balanced differential command // Noise on both lines cancels in differential input

Example 4: Arbitrary Waveform Generation with DMA

Design Guidelines

Resolution and Accuracy

Output Buffer Considerations

• Output Impedance: Typically 10-100Ω, varies with frequency and load
• Drive Capability: Limited current output (~10mA max), use buffer for heavy loads
• Capacitive Load: Maximum ~100pF without oscillation, add series resistor for higher capacitance
• Filtering: Add RC low-pass filter to remove switching artifacts (e.g., 1kΩ + 10nF for audio)

Voltage Reference Options

Reference Selection:

• VDDANA (Default): DAC output referenced to analog supply, simple but supply noise affects output
• External VREF: Precision external reference (e.g., 2.5V) for accurate voltage generation
• Internal Bandgap: Some devices offer internal 1.0V or 2.048V reference for stability
• Buffered Reference: Use reference buffer to reduce loading and improve accuracy

Update Rate and Throughput

// Maximum update rates (device-dependent): // SAM E5x/E7x: Up to 1 MSPS (1 μs per update) // SAM C2x: Up to 350 kSPS (2.86 μs per update) // Update rate limited by: // 1. DAC settling time (~1-3 μs) // 2. CPU/DMA transfer speed // 3. Application sample rate requirements // For high-speed waveforms (>100 kHz): // - Use DMA for CPU-free updates // - Pre-calculate waveform samples // - Minimize ISR overhead // - Consider external DAC for >1 MSPS

Noise and Distortion

• Thermal Noise: Approximately 10-50 μVrms (device-dependent)
• Glitch Energy: Minimize by using monotonic DAC architecture
• THD (Total Harmonic Distortion): Typically -60 to -80 dB for audio applications
• SFDR (Spurious Free Dynamic Range): >70 dB typical at low frequencies
• PSRR (Power Supply Rejection): -40 to -60 dB, use clean analog supply

PCB Layout Best Practices

• Separate Grounds: Analog ground plane under DAC area, single-point connection to digital ground
• Short Traces: Keep DAC output traces short to minimize noise pickup
• Decoupling: 100nF + 10μF capacitors close to VDDANA pin
• Reference Decoupling: Low-ESR capacitor (1-10μF) on VREF pin if using external reference
• Isolation: Route DAC signals away from switching noise (PWM, digital clocks)
• Guard Traces: Surround sensitive DAC traces with grounded guard traces

Performance Optimization

Reducing Update Latency

Power Consumption Optimization

Glitch Minimization Techniques

• Double Buffering: Some devices support double-buffered updates to synchronize output changes
• Simultaneous Update: Update both DAC channels atomically in differential mode
• Ramp Transitions: For large step changes, ramp through intermediate values
• Deglitching Filter: External RC filter to smooth output transitions

Troubleshooting

Related Blocks

• [MCHP_OP_AMP] - Operational amplifier for DAC output buffering/scaling
• [MCHP_PGA] - Programmable gain amplifier for DAC output amplification
• [MCHP_ADC_CoreIndependent_PIC32C] - SAM ADC for feedback/measurement
• [MCHP_Timer_PIC32] - Timer for DAC update rate control
• [MCHP_DMA_SAM] - DMA for continuous waveform streaming [← Back to Analog Blocks]