Output Compare HW Block Icon
The MCHP_OC_HW block provides hardware-based output generation using the Output Compare (OC) peripheral. It generates PWM signals, toggles outputs, or creates precise timing events based on timer comparisons with no CPU overhead during normal operation.

The MCHP_OC_HW block provides hardware-based output generation using the Output Compare (OC) peripheral. It generates PWM signals, toggles outputs, or creates precise timing events based on timer comparisons with no CPU overhead during normal operation.

Key Features

  • Hardware PWM generation - Automatic waveform generation without CPU intervention
  • Multiple OC modes - Toggle, set high, set low, dual compare PWM
  • Timer-based control - Rising/falling edges at specific timer counts
  • Remappable pins - PPS support for flexible pin assignment (device dependent)
  • Low latency - Direct hardware comparison, no interrupt overhead
  • Multiple channels - Up to 9 OC channels (device dependent)

Device Support

Device FamilyOC ChannelsPPS SupportNotes
dsPIC30F1-2Fixed pinsBasic OC functionality
dsPIC33F, PIC24H1-8Fixed pinsStandard OC peripheral
dsPIC33E, PIC24E1-9PPS remappableEnhanced features, flexible routing
dsPIC33C/CH/CK1-9PPS remappableHigh-speed timers available
dsPIC33A1-9PPS remappableUse PWM_HS_FEP for advanced PWM
PIC32MX/MZ/MK1-9PPS (32MK/MZ)32-bit timer support

Block Parameters

Channel Configuration

ParameterDescriptionValues
ChannelOC channel numbers to use1-9 (device dependent)
ModeOperating mode per channelSee OC Modes table below
Timer AssignmentWhich timer drives each OC channelTimer 2, 3, 4, 5 (device dependent)
PIN_OCxOutput pin mapping (PPS devices)Remappable pin selection

OC Operating Modes

ModeOCM BitsDescriptionCompare Registers Used
0000OC disabled-
3011Toggle output on compare matchOCxR
5101Set output high on compare, PR clearsOCxR
6110Set output low on compare, PR clearsOCxR
7111Dual compare (PWM mode)OCxR (rising), OCxRS (falling)

Block Input Datatype

The block supports 1 input datatype representation:

Input TypeRangeDescription
uint160 to Timer PRRaw timer counts for compare registers

Uint Raw Input (1 option)

Integer values transfer directly to OCxR/OCxRS registers—no runtime computation. Users handle scaling from physical units to timer counts.

Scaling formula: Compare_counts = Time_seconds × (FCY / Prescaler)

Hardware Considerations: dsPIC30F/33F/33E/33C lack hardware FPU—use fixed-point arithmetic in time-critical loops. dsPIC33A has hardware FPU. PIC32 devices have hardware FPU.

Implementation Details

Register Configuration (dsPIC)

// OCxCON1 register - Control register 1
OCxCON1bits.OCM = mode;        // 0-7 (operating mode)
OCxCON1bits.OCTSEL = timer_sel; // Timer source selection (0-3)
OCxCON1bits.OCSIDL = 0;        // Continue in idle mode

// Compare registers
OCxR  = rising_edge_count;     // Primary compare (rising edge in PWM)
OCxRS = falling_edge_count;    // Secondary compare (duty cycle in PWM)

// Timer selection encoding
// 0: Timer2, 1: Timer3, 2: Timer4, 3: Timer5

PWM Generation (Mode 7)

In PWM mode (Mode 7), the OC peripheral operates as follows:

  • OCxR sets the rising edge of the PWM pulse
  • OCxRS sets the falling edge (determines duty cycle)
  • Timer PR register sets the PWM period
  • Resolution depends on timer prescaler and frequency
// PWM Mode 7 timing diagram
Timer Count:  0 -----> OCxR -----> OCxRS -----> PR -----> 0
Output:       |        ↑            ↓            |
              LOW      HIGH         LOW          LOW

Duty Cycle = (OCxRS - OCxR) / PR
Frequency = FCY / (Prescaler × PR)

Pin Mapping

For remappable (PPS) devices:

// Example PPS configuration for OC1 on RP6 (dsPIC33E)
_RP6R = 0b010010;  // Route OC1 to RP6
// Block handles PPS automatically based on PIN_OCx parameter

For fixed-pin devices:

  • OC1 → Fixed pin (e.g., RC2 on dsPIC33F)
  • OC2 → Fixed pin (e.g., RC1 on dsPIC33F)
  • Refer to device datasheet for pin assignments

Block Usage Examples

Example 1: Simple PWM Generation

Application: Generate 20 kHz PWM with 50% duty cycle

% Block parameters
Channel: 1
Mode: 7              % PWM mode
Timer: Timer2 configured for 20 kHz period

% Timer configuration (assuming 60 MHz FCY)
% PR2 = 60,000,000 / (1 × 20,000) - 1 = 2999
% OCxR = 0 (PWM starts at timer reset)
% OCxRS = 1500 (50% duty cycle)

% Simulink model
[20kHz Clock][MCHP_TIMER_Config: Timer2, PR=2999]
[Duty Cycle Input: 1500][MCHP_OC_HW: Channel 1, Mode 7]

Example 2: Synchronized Multi-Phase Outputs

Application: Three-phase inverter control with 120° phase shifts

% Block parameters
Channel: [1 2 3]
Mode: [3 3 3]        % Toggle mode for all channels
Timer: [2 2 2]       % All use Timer2 for synchronization

% Timer configuration for 60 Hz output
% PR2 configured for 60 Hz base frequency
% OCxR values set for 120° phase offsets:
OC1R = 0             % Phase A at 0°
OC2R = PR2/3         % Phase B at 120°
OC3R = 2*PR2/3       % Phase C at 240°

% This creates 3 square waves with 120° spacing

Example 3: Precise One-Shot Pulse

Application: Generate a 10 µs pulse for trigger signal

% Block parameters
Channel: 1
Mode: 5              % Set high on compare, PR clears
Timer: Timer3 with 1:1 prescaler (16.67 ns resolution @ 60 MHz)

% For 10 µs pulse:
% OCxR = 600 (10 µs / 16.67 ns)
% PR3 = 1200 (20 µs period, allowing for 10 µs high + 10 µs low)

% Connect enable signal to start/stop pulse generation

Example 4: Variable Duty Cycle PWM

Application: Motor speed control with duty cycle input

% Block setup
Channel: 1
Mode: 7              % Dual compare PWM
Timer: Timer2 @ 20 kHz

% Simulink model structure
[Speed Command 0-100%] → [Gain: PR2/100] → [Data Type: uint16]
[MCHP_OC_HW Channel 1 RS input]

% OCxR = 0 (fixed rising edge)
% OCxRS = dynamic (0 to PR2 based on speed command)
% This creates 0-100% duty cycle PWM

Timing and Synchronization

Resolution and Frequency Limits

Timer PrescalerResolution @ 60 MHzMax FrequencyTypical Use Case
1:116.67 ns30 MHzHigh-speed PWM, precise timing
1:8133.3 ns3.75 MHzStandard PWM (10-100 kHz)
1:641.067 µs468 kHzLow-frequency PWM, servo control
1:2564.267 µs117 kHzVery low frequency applications

Synchronization with Other Peripherals

        Phase-shifted waveforms use same timer with different OCxR values
        Complementary outputs for bridge drivers
        Coordinated multi-axis motion control

Troubleshooting

Common Issues

No Output Signal

  • Check pin configuration: Verify PPS routing or fixed pin assignment
  • Verify timer operation: Ensure timer is running and not held in reset
  • Check OCM bits: Mode must be non-zero
  • TRIS register: Pin must be configured as output (block handles this)

Incorrect Frequency/Duty Cycle

  • Timer PR value: Verify timer period register calculation
  • OCxR/OCxRS values: Check compare register values are within 0 to PR
  • Timer prescaler: Confirm prescaler setting matches calculations
  • Clock source: Verify FCY (instruction cycle frequency)

Glitches or Irregular Output

  • Register update timing: In PWM mode, update OCxRS (not OCxR) for glitch-free changes
  • Shadow register: OCxRS is double-buffered, updates occur at period boundary
  • Simultaneous changes: Disable interrupts if updating multiple registers

See Also

Application Notes