SPI Master/Slave - Communication Block

dsPIC30F dsPIC33F dsPIC33E dsPIC33C dsPIC33A PIC32

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BUS SPI Block The BUS SPI block configures and executes SPI (Serial Peripheral Interface) communication sequences as either Master or Slave. This block supports full-duplex serial communication using a graphical sequence builder for complex multi-device transactions with configurable clock modes.

Block Inputs/Outputs

Inputs: Dynamic based on SPI sequence configuration

Outputs: Dynamic based on SPI sequence configuration

Dynamic Port Configuration

Block inputs and outputs are created based on the SPI sequence you configure:

• Write Data actions with block input enabled create input ports
• Read Data actions create output ports with received data
• Data width (8/16/32-bit) is configurable per sequence action

Block Input/Output Datatype

Supported Device Families

Block Parameters

Clock Modes (CPOL/CPHA)

SPI supports four clock modes based on clock polarity (CPOL) and phase (CPHA):

Select the mode matching your slave device’s requirements. Mode 0 and Mode 3 are most common.

Clock Frequency

Clock frequency is configured in the Initial Configuration action. The actual frequency depends on:

dsPIC (Standard):

• Primary prescaler: 1:1, 1:4, 1:16, 1:64
• Secondary prescaler: 1:1 to 1:8
• FSCK = FCY / (Primary × Secondary)

dsPIC33C/A (DOS-01482):

• 13-bit BRG divider
• FSCK = FSPI / (2 × BRG)

PIC32 (DOS-01329):

• 13-bit BRG divider
• FSCK = FSPI / (2 × (BRG + 1))

SAM (SERCOM):

• 8-bit BAUD register
• FSCK = GCLK / (2 × (BAUD + 1))

Implementation Details

Master vs Slave Mode

Master Mode:

• Generates SCK clock signal
• Controls SS (Slave Select) lines
• Initiates all transfers
• Can disable SCK output if unused

Slave Mode:

• Receives SCK from external master
• Responds when SS is asserted
• SS enable option for synchronization

DMA Support

DMA availability varies by device:

Enhanced Buffer Mode

Many SPI peripherals support enhanced buffer mode:

• dsPIC33E/F: 8-level FIFO buffer
• PIC32: Configurable FIFO depth
• Reduces interrupt overhead for multi-byte transfers

Pin Constraints (SAM SERCOM)

SAM SERCOM peripherals have specific PAD constraints for SPI:

The block validates pin combinations and warns if incompatible PADs are selected.

Usage Examples

Example 1: Read SPI Flash ID

Read JEDEC ID from SPI Flash:

1. Initial Configuration (10 MHz, Mode 0, Master)
2. Set Pin: SS → 0 (assert)
3. Write Data: 0x9F (JEDEC ID command)
4. Read Data: 3 bytes → Output "FlashID"
5. Set Pin: SS → 1 (deassert)

Example 2: Write to SPI DAC

Write 16-bit value to DAC:

1. Initial Configuration (5 MHz, Mode 0, 16-bit)
2. Set Pin: SS → 0
3. Write Data: [Config | Value] (from block input)
4. Set Pin: SS → 1

Example 3: Full-Duplex ADC Read

Simultaneous write command and read result:

1. Initial Configuration (1 MHz, Mode 0)
2. Set Pin: CS → 0
3. Write/Read: Write 0x00, Read 2 bytes → "ADCValue"
4. Set Pin: CS → 1

Example 4: Multi-Slave Configuration

Communicate with multiple SPI devices:

1. Initial Configuration (Mode 0)
2. Set Pin: SS1 → 0
3. Write/Read with Device 1
4. Set Pin: SS1 → 1
5. Update Configuration (Mode 3)  // Different device needs different mode
6. Set Pin: SS2 → 0
7. Write/Read with Device 2
8. Set Pin: SS2 → 1

Troubleshooting

No SPI Communication

Problem: No data on SPI bus.

Solutions:

• Verify SDI, SDO, SCK pin assignments match hardware
• Check SS signal - must be asserted (typically low) for slave
• Verify clock frequency is within slave device limits
• Confirm clock mode (CPOL/CPHA) matches slave requirements

Corrupted Data

Problem: Data received is incorrect or shifted.

Solutions:

• Check clock mode (CPOL/CPHA) matches slave device
• Verify data width (8/16/32-bit) matches slave
• Check for noise on SPI lines (reduce speed or add filtering)
• Verify bit order (MSB/LSB first) matches slave

SAM SERCOM PIN Conflict

Problem: “Pin mapping issue” warning.

Solutions:

• SERCOM SPI has PAD constraints - not all pin combinations valid
• Review valid PAD combinations table above
• Use different pins or SERCOM instance

DMA Not Working

Problem: DMA mode selected but transfers fail.

Solutions:

• Verify device supports SPI DMA (see table above)
• Check DMA channel availability (other blocks may use DMA)
• dsPIC33CK/CH does not support SPI DMA - use interrupt mode

Clock Frequency Mismatch

Problem: Actual frequency differs from requested.

Solutions:

• SPI frequency is derived from prescalers - not all frequencies achievable
• Check compilation output for actual achieved frequency
• Adjust requested frequency to one achievable with available dividers

See Also

• Communication Blocks Overview
• I2C Block
• UART Configuration
• CAN Configuration