TCC PWM

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Timer/Counter for Control (TCC) PWM peripheral for SAM microcontrollers. Features advanced pattern generation, complementary outputs with dead-time, and fault protection for motor control.

Overview

The TCC PWM block configures the Timer/Counter for Control (TCC) peripheral on SAME5x, SAMC2x, and SAMD2x microcontrollers. TCC modules provide advanced PWM generation with:

• Complementary output pairs (WO0+WO4, WO1+WO5, etc.) with programmable dead-time
• Output matrix (OTMX) to map compare channels (CCx) to waveform outputs (WOx)
• Pattern generator for BLDC motor commutation (hardware-assisted 6-step)
• Recoverable and non-recoverable faults with configurable output states
• Dual-slope (center-aligned) and single-slope (left-aligned) counting
• Dithering for enhanced PWM resolution
• Capture/Compare for position sensing and multi-axis synchronization

The TCC peripheral is optimized for motor control, offering features not available in basic Timer/Counter (TC) modules.

When to use:

• Motor control on SAM E5x, SAM D5x, SAM C2x, or SAM D2x devices
• BLDC commutation with hardware-assisted pattern generation
• Complementary outputs with dead-time for half-bridge/full-bridge drivers
• Applications requiring output matrix flexibility (OTMX) for complex topologies

When NOT to use:

• SAM E7x, SAM S7x, or SAM V7x devices → use PWM SAM7x
• dsPIC devices → use PWM , PWM HighSpeed , or PWM HS FEP

Block Dialog

Signals Tab

Initial Values Tab

Block Inputs Tab

Ports

Inputs

Outputs

The block has no outputs. PWM signals are generated directly on configured WOx pins.

Parameters

Main Tab

Signals Tab

Initial Values Tab

Block Inputs Tab

TCC Instance Availability

Notes:

• TCC0 typically has the most features (6 compare channels, 8 outputs)
• Some devices have additional TCC3/TCC4 with reduced capabilities
• WO outputs are remappable via pin multiplexing (up to 2-4 options per WO)

Output Matrix (OTMX)

The OTMX parameter controls how Compare Channels (CC0-CC5) drive Waveform Outputs (WO0-WO7):

Usage:

• Default: Standard 6-output motor control (3 complementary pairs)
• Variant 1: Modulo-3 wrapping (for 3-phase systems with fewer CC channels)
• Variant 2: All WO outputs mirror CC0 (synchronized multi-motor control)
• Variant 3: WO0 independent, WO1-7 mirror CC1 (master-slave topology)

// Clock enable (chip-specific GCLK assignment)
GCLK_REGS->GCLK_PCHCTRL[idx_GCLK_PCHCTRLn] = GCLK_PCHCTRL_GEN(GCLK_idx) | GCLK_PCHCTRL_CHEN_Msk;

// Waveform generation mode
TCC_REGS->TCC_WAVE = TCC_WAVE_WAVEGEN_NPWM;      // Left-aligned
                   // or TCC_WAVE_WAVEGEN_DSBOTTOM; // Center-aligned
                   | TCC_WAVE_POLx_Msk;            // Polarity per channel
                   | TCC_WAVE_SWAPx_Msk;           // Swap complementary pairs

// Period and duty cycle
TCC_REGS->TCC_PER = PER_value;
TCC_REGS->TCC_CC[0..N] = CCx_value;

// Dead-time and output matrix
TCC_REGS->TCC_WEXCTRL = TCC_WEXCTRL_OTMX(OTMX)
                      | TCC_WEXCTRL_DTIENx_Msk      // Dead-time enable
                      | TCC_WEXCTRL_DTLS(DTLS)
                      | TCC_WEXCTRL_DTHS(DTHS);

// Output override (pattern generator)
TCC_REGS->TCC_PATT = (override_enable << 0) | (output_value << 8);

// Invert selected outputs
TCC_REGS->TCC_DRVCTRL = TCC_DRVCTRL_INVENx_Msk;

// Start counter
TCC_REGS->TCC_CTRLA = TCC_CTRLA_ENABLE_Msk
                    | TCC_CTRLA_PRESCALER_DIVx
                    | TCC_CTRLA_RUNSTDBY_Msk;

TCC_REGS->TCC_PERBUF = new_period;   // Buffered period
TCC_REGS->TCC_CCBUF[x] = new_cc;     // Buffered compare
// Updates applied at next period boundary

TCC_REGS->TCC_CCB[x] = new_cc;       // Direct compare update
// Takes effect immediately (may cause glitches)

// Read-modify-write to preserve OTMX and DTIEN settings
tmp_reg = TCC_REGS->TCC_WEXCTRL;
tmp_reg = (tmp_reg & ~TCC_WEXCTRL_DTHS_Msk) | TCC_WEXCTRL_DTHS(new_dths);
tmp_reg = (tmp_reg & ~TCC_WEXCTRL_DTLS_Msk) | TCC_WEXCTRL_DTLS(new_dtls);
TCC_REGS->TCC_WEXCTRL = tmp_reg;

Notes

SAME5x vs SAMD2x Differences

Code Generation Adaptation: The TLC file detects chip family via ::isSAMD2_DA1 flag and generates appropriate register names (TCC_CCB vs TCC_CCBUF).

Dead-Time Limitations

• Dead-time resolution: 8 bits (0-255 prescaler ticks)
• Applied globally to all channels (not per-channel)
• Maximum dead-time depends on prescaler (e.g., 21.3 µs at 120 MHz with DIV1)
• Dead-time is inserted after polarity inversion (INVEN) but before pattern override

Output Override Priority

When pattern generator (PATT register) is active:

1. Override replaces PWM generator output
2. Dead-time is not applied to overridden outputs
3. Polarity inversion (INVEN) is still applied

Safe Override Design:

% Ensure software dead-time in pattern logic
% Bad:  [WO0=1, WO4=1] -> both high-side and low-side ON!
% Good: [WO0=1, WO4=0] or [WO0=0, WO4=1]

Clock Configuration

The block automatically:

1. Selects fastest available GCLK (typically GCLK1 @ core frequency)
2. Calculates prescaler (1/2/4/8/16/64/256/1024) to fit MaxPeriod_s
3. Creates workspace variable PWMxmax = counter maximum value
4. Configures GCLK_PCHCTRL register for TCC clock routing

Multi-Instance Shared Resources: All TCC blocks using the same TCCREF must have identical:

• MaxPeriod_s (clock prescaler)
• WAVE_choice (waveform mode)
• OTMX (output matrix)

Compilation error if mismatch detected via MchpLocal2Global() validation.

Event System Integration

TCC can generate events (via TCC_EVCTRL) for:

• ADC trigger: Synchronize current sampling to PWM valley/peak
• Multi-axis sync: Lock multiple TCC instances to same timebase
• External fault: Connect comparator output to TCC fault input

Example (configured in PWM SAM7x, TCC similar concept):

TCC0_REGS->TCC_EVCTRL |= TCC_EVCTRL_OVFEO_Msk;  // Overflow event
// Route to ADC via EVSYS peripheral

Device Support

• SAM E5x (SAME54P/N/J, SAME53N/J, SAME51N/J 19/20)
• SAM D5x (SAMD51P/N/J/G 19/20)
• SAM C2x (SAMC21N/J/G/E 15/16/17/18)
• SAM D2x (SAMD21G/J/E 15/16/17/18)

Examples

Three-Phase BLDC Motor (SAME54)

% 20 kHz center-aligned PWM with 1 µs dead-time
TCCREF = 'TCC 0';
WAVE_choice = 'Center aligned PWM';
MaxPeriod_s = 1/20e3;  % 50 µs
OTMX = 'Default';

% Pin assignments (3 complementary pairs)
WO0 = 'PA08 / Pin[33]';  % Phase U High
WO4 = 'PA16 / Pin[66]';  % Phase U Low
WO1 = 'PA09 / Pin[34]';  % Phase V High
WO5 = 'PA17 / Pin[67]';  % Phase V Low
WO2 = 'PA10 / Pin[35]';  % Phase W High
WO6 = 'PA18 / Pin[68]';  % Phase W Low

InitPeriod_s = 1/20e3;
InitDutyCycle_s = [25e-6, 25e-6, 25e-6];  % 50% duty
InitDeadTimeH_s = 1e-6;
InitDeadTimeL_s = 1e-6;

% Runtime control
BlockInput_DutyCycle = 'a Floating Point input within range [-1 1]';
BlockInput_VectorScalar = 'Vectors (grouped by function)';

% Connect 3-element duty cycle vector from FOC controller

Synchronized Dual Motor (SAMC21)

% Two motors with phase-locked operation (OTMX Variant 2)
TCCREF = 'TCC 0';
OTMX = 'Variant 2';  % All WO outputs follow CC0

WO0 = 'PA08 / Pin[33]';  % Motor 1 Phase U
WO1 = 'PA09 / Pin[34]';  % Motor 1 Phase V
WO2 = 'PA10 / Pin[35]';  % Motor 1 Phase W
WO4 = 'PA16 / Pin[66]';  % Motor 2 Phase U
WO5 = 'PA17 / Pin[67]';  % Motor 2 Phase V
WO6 = 'PA18 / Pin[68]';  % Motor 2 Phase W

% Single duty cycle input controls both motors identically
BlockInput_DutyCycle = 'a Floating Point input within range [0 1]';

Emergency Shutdown via Override (Immediate)

% Force all outputs LOW on fault (PATT register direct write)
TCCREF = 'TCC 0';
BlockInput_OutputOverride = ' RAW PATT register ; 8 LSB is override active ; 8MSB is out val (Imm)';

% MATLAB Function block:
function patt_reg = shutdown_control(fault)
    if fault
        % Bits 0-7: override enable (all WO outputs)
        % Bits 8-15: output values (all LOW)
        patt_reg = uint16(hex2dec('00FF'));
    else
        patt_reg = uint16(0);  % Normal PWM operation
    end
end

BLDC Commutation with Pattern Generator

% Hardware-assisted 6-step commutation (pattern table in MCU)
TCCREF = 'TCC 0';
BlockInput_OutputOverride = ' Override Activation & pin ouptut value block inputs';

% MATLAB Function for 6-step pattern:
function [override, output] = commutation(hall_state)
    % Hall state 0-7, only 1-6 valid
    patterns = uint8([
        0b00000000;  % Invalid
        0b00100001;  % Hall 1: WO0=1, WO5=1
        0b00001100;  % Hall 2: WO2=1, WO3=1
        0b00101100;  % Hall 3: WO2=1, WO3=1, WO5=1
        0b00110010;  % Hall 4: WO1=1, WO4=1, WO5=1
        0b00110001;  % Hall 5: WO0=1, WO4=1, WO5=1
        0b00011010;  % Hall 6: WO1=1, WO3=1, WO4=1
        0b00000000   % Invalid
    ]);
    
    override = uint8(63);  % Enable override for WO0-5 (0b00111111)
    output = patterns(hall_state + 1);
end

Programmatic Setup

% Add block to model
add_block('MCHP_Blockset/PWM IO/PWM TCC', [mdl '/TCC_PWM']);

% Configure key parameters
set_param([mdl '/TCC_PWM'], 'TCCREF', 'TCC 0');
set_param([mdl '/TCC_PWM'], 'MaxPeriod_s', '1e-3');
set_param([mdl '/TCC_PWM'], 'InitPeriod_s', '1e-3');
set_param([mdl '/TCC_PWM'], 'InitDutyCycle_s', '0.5e-3');

Related Blocks

• PWM SAM7x — SAM7x PWMC peripheral (higher channel count, more fault options)
• MCHP_ADC_SAM — SAM ADC with TCC event synchronization
• MCHP_QEI_SAM — Quadrature encoder input (Hall sensor interface)
• MCHP_TC_PWM — Basic Timer/Counter PWM (no dead-time, simpler)