The Interrupt block creates interrupt-driven subsystems by connecting peripheral interrupt sources to Simulink triggered subsystems. The block automatically manages interrupt vector configuration, priority levels, and timing synchronization. Key Capabilities: - Automatic interrupt detection - Discovers all peripheral interrupts in model - Dynamic interrupt list - Popup shows only available interrupts from active peripherals - Priority management - Configure interrupt priority levels (device-dependent) - Multiple timing modes - Base rate, periodic trigger, or hardware timer-based - Context preservation - Automatic FPU context save/restore (PIC32 with FPU)
Interrupt Sources
Peripheral Interrupts (Auto-detected)
The block automatically detects interrupts from peripheral blocks in your model:
| Peripheral | Interrupt Types | Example Usage |
|---|
| ADC | • Conversion complete | • Individual converter done |
| PWM | • Period match | • Trigger event |
| QEI | • Position counter overflow | • Index pulse |
| UART | • RX data ready | • TX buffer empty |
| SPI | • Transfer complete | • Buffer full/empty |
| I2C | • Master/slave events | • Address match |
| CAN | • Message received | • TX complete |
| Timer | • Period match | • Compare match |
User-Defined Interrupts
Peripheral blocks can define custom interrupts using MCHP_USER_INTERRUPTS parameter:
// In peripheral block RTWdata
Parameters format:
VectorName(name) % If new vector needed
Config_BitSet(IECx=value) % Interrupt enable bits
RegisterReadClear(IFSx) % Flag clear register
Priority(level) % Fixed priority or -1 for user config
Block Parameters
Interrupt Selection
| Parameter | Description | Values |
|---|
| Interruption | Select interrupt source from dynamic list of available peripheral interrupts. | • Not defined |
| IntPriority | Interrupt priority level (if configurable). Higher number = higher priority. | 1-7 (dsPIC/PIC24) |
| FPUNoSave | (PIC32 with FPU only) | Disable automatic FPU context save if ISR does not use floating-point operations (optimization). |
| StartupExecute | Execute subsystem once during initialization (before first interrupt). | on / off |
Timing Configuration
| Parameter | Description | Use Case |
|---|
| Triggered_Sub_TimeSource | Timing reference for triggered subsystem sample time. | • |
| TrigsPeriod | (Periodic trigs mode) | Subsystem sample time when using periodic trigger mode. |
| TIMER_Resolution | (Hardware timer mode) | Select timer prescaler for desired resolution and max period. |
Device-Specific Interrupt Configuration
dsPIC30F/33F/33E/33C/33A
| Feature | Configuration | Notes |
|---|
| Priority Levels | 1-7 (7 = highest) | Default is level 4 |
| Nesting | Automatic if priorities differ | Higher priority can preempt lower |
| Vector Table | Auto-managed by blockset | IVT and AIVT support |
| Context Save | W0-W15, RCOUNT, SR | Automatic register preservation |
PIC32 (MIPS)
| Feature | Configuration | Notes |
|---|
| Priority Levels | 1-7 (7 = highest) | Sub-priority 0-3 also available |
| Shadow Registers | Automatic if configured | Fast context switch (no save) |
| FPU Context | Optional save/restore | Only if FP ops used in ISR |
| Multi-Vector Mode | Enabled by blockset | Each peripheral has dedicated vector |
SAM (ARM Cortex-M)
| Feature | Configuration | Notes |
|---|
| Priority Levels | 0-15 (0 = highest) | NVIC priority grouping |
| Tail-Chaining | Automatic hardware optimization | Back-to-back ISRs without full context restore |
| Late Arrival | Hardware-managed preemption | Higher priority can preempt during stacking |
| FPU Lazy Stacking | Conditional FP context save | Only saved if FP registers used |
Examples
Example 1: ADC Interrupt-Driven Current Loop
// PWM triggers ADC, ADC interrupt executes control loop
Simulink Model:
1. Add PWM_HS block with ADC trigger output
2. Add ADC block with interrupt enabled
3. Add Interrupt block
4. Configure interrupt block:
Interruption: 'ADC1 - Conversion Complete'
Triggered_Sub_TimeSource: 'is derived from model base rate'
IntPriority: 7 (highest - critical for motor control)
5. Create triggered subsystem connected to interrupt block
6. Add current control algorithm inside subsystem
Result: Current loop executes synchronously with PWM/ADC
Example 2: UART Receive Interrupt
// Process received data asynchronously
Configuration:
Interruption: 'UART1 - RX'
Triggered_Sub_TimeSource: 'is derived from trigs; trigs must be periodic'
TrigsPeriod: 1e-3 % 1 ms assumed for timing (actual rate is async)
IntPriority: 3 (medium priority)
StartupExecute: on (initialize buffers)
Subsystem:
- Read UART data from peripheral block
- Parse protocol
- Update command registers
Example 3: Hardware Timer Periodic Interrupt
// Custom periodic task independent of base rate
Configuration:
Interruption: 'User Timer1' (created by peripheral block)
Triggered_Sub_TimeSource: 'is derived from a hardware timer'
TIMER_Resolution: 'Resol: 32us - MaxPer: 2.1s' (prescaler 256)
IntPriority: 5
Result:
- Dedicated timer allocated automatically
- Interrupt triggers at specified rate
- Independent of Simulink sample times
Example 4: QEI Position Overflow Event
// Extend encoder range with software counter
Configuration:
Interruption: 'QEI1 - Position Counter Overflow'
Triggered_Sub_TimeSource: 'is derived from model base rate'
IntPriority: 6 (high - timing critical)
Subsystem Logic:
if (QEI_DIR == FORWARD)
ExtendedPosition += 65536;
else
ExtendedPosition -= 65536;
end
Timing Modes Explained
Mode 1: Derived from Model Base Rate
- Subsystem sample time = model base rate
- Timing analysis uses base rate for schedulability
- Best for interrupts synchronized with main control loop
- Example: ADC conversion complete after PWM trigger
Mode 2: Derived from Periodic Trigs
- User specifies expected interrupt rate in TrigsPeriod
- Allows timing analysis for asynchronous interrupts
- Subsystem scheduled assuming periodic behavior
- Example: UART receive (assume max message rate)
Mode 3: Hardware Timer-Based
- Dedicated timer resource automatically allocated
- Timer configured with selected prescaler
- True periodic interrupt independent of Simulink rates
- Example: Custom 1 kHz update loop
Troubleshooting
| Problem | Cause | Solution |
|---|
| Interrupt not listed | Peripheral block not in model or interrupt not enabled | Add peripheral block, enable interrupt in peripheral config |
| Subsystem never executes | Interrupt source not configured correctly | Verify peripheral interrupt enable, check flag register |
| System hangs in ISR | Interrupt flag not cleared | Ensure RegisterReadClear is correct in peripheral definition |
| Priority not working | Architecture limitation or incorrect setting | Check device datasheet for valid priority range |
| FPU corruption (PIC32) | FPUNoSave enabled but FP ops in ISR | Disable FPUNoSave or remove FP operations from ISR |
Keep ISR execution time short - long ISRs can cause overload
Higher priority ISRs can preempt lower priority - ensure reentrancy
Hardware timer mode consumes one timer resource
StartupExecute useful for initializing communication protocols
See Also
- [MCHP_Scheduler_Options] - Multitasking scheduler configuration
- [MCHP_Master] - Clock and device configuration
- [MCHP_ADC_Universal] - ADC interrupt sources
- [MCHP_PWM_HS_FEP] - PWM event interrupts