Interrupt

dsPIC30F dsPIC33F dsPIC33E dsPIC33C dsPIC33A PIC32

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The Interrupt block creates interrupt-driven subsystems by connecting peripheral interrupt sources to Simulink triggered subsystems. The block automatically manages interrupt vector configuration, priority levels, and timing synchronization. Key Capabilities: - Automatic interrupt detection - Discovers all peripheral interrupts in model - Dynamic interrupt list - Popup shows only available interrupts from active peripherals - Priority management - Configure interrupt priority levels (device-dependent) - Multiple timing modes - Base rate, periodic trigger, or hardware timer-based - Context preservation - Automatic FPU context save/restore (PIC32 with FPU)

When to use:

When to use:

• Hardware event must trigger Simulink subsystem (ADC done, UART RX, encoder overflow)
• Need lowest latency response to peripheral event (faster than polling)
• PWM-synchronized control loop (ADC interrupt after PWM trigger)
• Asynchronous communication (UART/SPI/I2C receive events)
• Extending encoder range with overflow/underflow interrupts

When NOT to use:

• Timer-based periodic tasks suffice — use Simulink sample times instead
• Polling peripheral status is fast enough for application timing
• Adding complexity without latency benefit — interrupts add overhead
• Peripheral block does not define interrupt source (check dropdown list)

Block Dialog

Advanced Tab

Parameters

Interrupt Selection

Changed in v3.63.x — The legacy fire-every-step fallback has been removed. A triggered subsystem connected to an Interrupt block whose source is never raised at run-time is now reported as a build-time configuration error instead of silently firing at the model base rate. If an older model relied on that behaviour, connect the subsystem to a Timer-based trigger instead, or mark StartupExecute=on when a one-shot initialisation is all that is needed. The Change Notification (CN) callback also emits a warning when EVT_EN is empty but at least one channel is configured, to catch the same misconfiguration on CN-driven interrupts.

Timing Configuration

Interrupt Sources

Peripheral Interrupts (Auto-detected)

The block automatically detects interrupts from peripheral blocks in your model:

User-Defined Interrupts

Peripheral blocks advertise themselves to the Interrupt block through the MCHP_USER_INTERRUPTS mask parameter. The Interrupt block scans every block in the model with a non-empty MCHP_USER_INTERRUPTS field and aggregates the entries into the Interruption popup.

Declaration format — one or more semicolon-separated entries, each with four {…} fields:

{InterruptFlagRef}{ShortDescription}{LongDescription}{Parameters};

Parameter tokens (inside the fourth field)

Example — Change Notification (single channel) (from MCHP_CN_Callback.m):

NewMask.Values.MCHP_USER_INTERRUPTS = ...
    ['{CN1IE}{CN1}{Change Notification - 1}{' NewMask.Values.IntPriority '};'];

Because the fourth field is just a number, it is treated as Priority(N); VectorName is therefore empty → the Interrupt block does not emit a duplicate vector for this entry.

Driver / User ISR Coexistence (dsPIC / PIC32)

Peripheral drivers and user-defined Interrupt blocks can request the same vector. The blockset resolves this with a three-tier architecture that is selected automatically from the MCHP_USER_INTERRUPTS declaration:

Why it matters — mixing up the rules produces either (a) a linker error from two symbols claiming the same vector, or (b) a silent failure where the user subsystem is never called because the driver ISR does not know about it. The callback enforces this automatically — no user action required — but when writing a new peripheral TLC you must follow the same conventions.

Device-Specific Interrupt Configuration

dsPIC30F/33F/33E/33C/33A

PIC32 (MIPS)

SAM (ARM Cortex-M)

Timing Modes Explained

Mode 1: Derived from Model Base Rate

• Subsystem sample time = model base rate
• Timing analysis uses base rate for schedulability
• Best for interrupts synchronized with main control loop
• Example: ADC conversion complete after PWM trigger

Mode 2: Derived from Periodic Trigs

• User specifies expected interrupt rate in TrigsPeriod
• Allows timing analysis for asynchronous interrupts
• Subsystem scheduled assuming periodic behavior
• Example: UART receive (assume max message rate)

Mode 3: Hardware Timer-Based

• Dedicated timer resource automatically allocated
• Timer configured with selected prescaler
• True periodic interrupt independent of Simulink rates
• Example: Custom 1 kHz update loop

Examples

Programmatic Setup

% Add block to model
add_block('MCHP_Blockset/System Functions/Interrupt', [mdl '/ISR']);

% Configure key parameters
set_param([mdl '/ISR'], 'Interruption', 'ADC1 Interrupt');
set_param([mdl '/ISR'], 'IntPriority', '6');

Example 1: ADC Interrupt-Driven Current Loop

// PWM triggers ADC, ADC interrupt executes control loop

Simulink Model:
1. Add PWM_HS block with ADC trigger output
2. Add ADC block with interrupt enabled
3. Add Interrupt block
4. Configure interrupt block:
   Interruption: 'ADC1 - Conversion Complete'
   Triggered_Sub_TimeSource: 'is derived from model base rate'
   IntPriority: 7  (highest - critical for motor control)

5. Create triggered subsystem connected to interrupt block
6. Add current control algorithm inside subsystem

Result: Current loop executes synchronously with PWM/ADC

Example 2: UART Receive Interrupt

// Process received data asynchronously

Configuration:
   Interruption: 'UART1 - RX'
   Triggered_Sub_TimeSource: 'is derived from trigs; trigs must be periodic'
   TrigsPeriod: 1e-3  % 1 ms assumed for timing (actual rate is async)
   IntPriority: 3  (medium priority)
   StartupExecute: on  (initialize buffers)

Subsystem:
- Read UART data from peripheral block
- Parse protocol
- Update command registers

Example 3: Hardware Timer Periodic Interrupt

// Custom periodic task independent of base rate

Configuration:
   Interruption: 'User Timer1'  (created by peripheral block)
   Triggered_Sub_TimeSource: 'is derived from a hardware timer'
   TIMER_Resolution: 'Resol: 32us - MaxPer: 2.1s'  (prescaler 256)
   IntPriority: 5

Result:
- Dedicated timer allocated automatically
- Interrupt triggers at specified rate
- Independent of Simulink sample times

Example 4: QEI Position Overflow Event

// Extend encoder range with software counter

Configuration:
   Interruption: 'QEI1 - Position Counter Overflow'
   Triggered_Sub_TimeSource: 'is derived from model base rate'
   IntPriority: 6  (high - timing critical)

Subsystem Logic:
if (QEI_DIR == FORWARD)
    ExtendedPosition += 65536;
else
    ExtendedPosition -= 65536;
end

Troubleshooting

        Keep ISR execution time short - long ISRs can cause overload
        Higher priority ISRs can preempt lower priority - ensure reentrancy
        Hardware timer mode consumes one timer resource
        StartupExecute useful for initializing communication protocols

Related Blocks

• MCHP_Scheduler_Options - Multitasking scheduler configuration
• MCHP_Master - Clock and device configuration
• MCHP_ADC_Universal - ADC interrupt sources
• MCHP_PWM_HS_FEP - PWM event interrupts