Interrupt

dsPIC30F dsPIC33F dsPIC33E dsPIC33C dsPIC33A PIC32

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The Interrupt block creates interrupt-driven subsystems by connecting peripheral interrupt sources to Simulink triggered subsystems. The block automatically manages interrupt vector configuration, priority levels, and timing synchronization. Key Capabilities: - Automatic interrupt detection - Discovers all peripheral interrupts in model - Dynamic interrupt list - Popup shows only available interrupts from active peripherals - Priority management - Configure interrupt priority levels (device-dependent) - Multiple timing modes - Base rate, periodic trigger, or hardware timer-based - Context preservation - Automatic FPU context save/restore (PIC32 with FPU)

When to use:

When to use:

• Hardware event must trigger Simulink subsystem (ADC done, UART RX, encoder overflow)
• Need lowest latency response to peripheral event (faster than polling)
• PWM-synchronized control loop (ADC interrupt after PWM trigger)
• Asynchronous communication (UART/SPI/I2C receive events)
• Extending encoder range with overflow/underflow interrupts

When NOT to use:

• Timer-based periodic tasks suffice — use Simulink sample times instead
• Polling peripheral status is fast enough for application timing
• Adding complexity without latency benefit — interrupts add overhead
• Peripheral block does not define interrupt source (check dropdown list)

Block Dialog

1. Main2. Advanced

Screenshots taken with chip 33AK512MPS512

Parameters

Interrupt Selection

Changed in v3.63.x — The legacy fire-every-step fallback has been removed. A triggered subsystem connected to an Interrupt block whose source is never raised at run-time is now reported as a build-time configuration error instead of silently firing at the model base rate. If an older model relied on that behaviour, connect the subsystem to a Timer-based trigger instead, or mark StartupExecute=on when a one-shot initialisation is all that is needed. The Change Notification (CN) callback also emits a warning when EVT_EN is empty but at least one channel is configured, to catch the same misconfiguration on CN-driven interrupts.

Timing Configuration

Interrupt Sources

The Interruption popup is built dynamically every time the dialog opens. It is populated from two passes over the model:

1. Phase 1 — Peripheral declarations. Every block whose mask exposes a non-empty MCHP_USER_INTERRUPTS parameter contributes one or more entries (ADC, PWM, UART, QEI, Timer Config, CN, Comparator, I2C/SPI sequence-Interrupt actions, …).
2. Phase 2 — Chip IVT database. After the peripheral pass, the callback queries MCHP_Fun.MCHP_IVT_FromDB(chipName) and appends every IVT vector defined for the actual target chip that has not already been claimed in Phase 1. These appear under the popup separator --- Chip Interrupt Vectors ---.

What ends up in the Interrupt block dialog therefore falls into three classes with very different responsibilities for the user.

The three classes of interrupts

Classes A and B both stem from MCHP_USER_INTERRUPTS; their distinction is only the value of Priority. Class C bypasses MCHP_USER_INTERRUPTS entirely.

Class A — chaining a user subsystem after the driver. This is the deliberate “hook” pattern: e.g. on a CN interrupt, the CN block writes the ISR (debounce, edge-detect, register read), and your wired Interrupt subsystem runs at the end of that same ISR — you only see the post-processed event. Same for SPI / I2C sequence-step interrupts, Comparator, UART RX/TX (Circular Buffer / DMA), DMA, and QEI in turn-counting mode. The chaining is automatic; the only signal that an entry is Class A is the locked priority field.

Implementation tiers. The hook is realised by three slightly different code-generation paths — Tier 1 inline for CN, Tier 2 callable function via MCHP_CallUserISR for UART / QEI / DMA, and Tier 3 hardcoded #ifdef Flag_… / func(); / #endif call-site for SPI / I2C / Comparator. From the user’s point of view all three are identical: pick the entry, wire the subsystem, the driver invokes it. See Driver / User ISR Coexistence below if you are authoring a new peripheral TLC.

What the block clears for you, by class

In other words: you almost never have to clear xxIF yourself — the Interrupt block does it on entry — unless the silicon has a separate sub-event flag that the IVT database does not surface. Class A: nothing to do, the driver gives you a post-processed event; Class B: fully managed end-to-end as long as the peripheral block declared its RegisterReadClear; Class C: may need extra clears that you have to add to the subsystem.

How peripherals declare interrupts — MCHP_USER_INTERRUPTS

Class A and Class B entries both come from the MCHP_USER_INTERRUPTS hidden mask parameter. The Interrupt block’s callback scans every block in the model with a non-empty value and concatenates them into one list.

Declaration format — one or more semicolon-separated entries, each with four {…} fields:

{InterruptFlagRef}{ShortDescription}{LongDescription}{Parameters};

Parameter tokens (inside the fourth field)

Example — Change Notification (single channel) (from MCHP_CN_Callback.m):

NewMask.Values.MCHP_USER_INTERRUPTS = ...
    ['{CN1IE}{CN1}{Change Notification - 1}{' NewMask.Values.IntPriority '};'];

The fourth field is a bare number ⇒ treated as Priority(N); VectorName is empty ⇒ Tier 1 inline (see below).

Driver / User ISR Coexistence (dsPIC / PIC32) — three tiers

When the same vector is needed by both the peripheral driver and a user-attached Interrupt block, the blockset selects one of three code-generation tiers automatically. This is an implementation detail of how Class A is realised; users do not pick it — it is fixed per peripheral.

Why this matters — declaring an interrupt in MCHP_USER_INTERRUPTS without wiring an Interrupt block is safe: it only adds an option to the dropdown. No IE bit is set and no ISR is emitted. The blockset enforces the tier rules automatically; you only need them when authoring a new peripheral TLC.

Which peripherals declare which class — quick reference

Anything else exposed by the silicon — CRC, NVM, ECC, CAN error vectors, unused DMA channels, secondary timers, etc. — does not go through any peripheral block and arrives via Phase 2 as a Class C — Raw Chip Vector under the --- Chip Interrupt Vectors --- separator.

When you would actually pick a Class A entry

• CN (digital edge-detect): the CN block does the debounce / pin-state read; your subsystem reacts to the cleaned event.
• I2C / SPI sequence-step Interrupt action: you placed the Interrupt step inside the bus sequence; your subsystem runs at that point of the transfer.
• Comparator: the analog comparator block reads CMSTAT and arms the next edge; your subsystem decides what to do with the event.

For those three, Class A is the normal way to use the interrupt, not an exception.

Device-Specific Interrupt Configuration

dsPIC30F/33F/33E/33C/33A

PIC32 (MIPS)

SAM (ARM Cortex-M)

Timing Modes Explained

Mode 1: Derived from Model Base Rate

• Subsystem sample time = model base rate
• Timing analysis uses base rate for schedulability
• Best for interrupts synchronized with main control loop
• Example: ADC conversion complete after PWM trigger

Mode 2: Derived from Periodic Trigs

• User specifies expected interrupt rate in TrigsPeriod
• Allows timing analysis for asynchronous interrupts
• Subsystem scheduled assuming periodic behavior
• Example: UART receive (assume max message rate)

Mode 3: Hardware Timer-Based

• Dedicated timer resource automatically allocated
• Timer configured with selected prescaler
• True periodic interrupt independent of Simulink rates
• Example: Custom 1 kHz update loop

Examples

Programmatic Setup

% Add block to model
add_block('MCHP_Blockset/System Functions/Interrupt', [mdl '/ISR']);

% Configure key parameters
set_param([mdl '/ISR'], 'Interruption', 'ADC1 Interrupt');
set_param([mdl '/ISR'], 'IntPriority', '6');

Example 1: ADC Interrupt-Driven Current Loop

// PWM triggers ADC, ADC interrupt executes control loop

Simulink Model:
1. Add PWM_HS block with ADC trigger output
2. Add ADC block with interrupt enabled
3. Add Interrupt block
4. Configure interrupt block:
   Interruption: 'ADC1 - Conversion Complete'
   Triggered_Sub_TimeSource: 'is derived from model base rate'
   IntPriority: 7  (highest - critical for motor control)

5. Create triggered subsystem connected to interrupt block
6. Add current control algorithm inside subsystem

Result: Current loop executes synchronously with PWM/ADC

Example 2: UART Receive Interrupt

// Process received data asynchronously

Configuration:
   Interruption: 'UART1 - RX'
   Triggered_Sub_TimeSource: 'is derived from trigs; trigs must be periodic'
   TrigsPeriod: 1e-3  % 1 ms assumed for timing (actual rate is async)
   IntPriority: 3  (medium priority)
   StartupExecute: on  (initialize buffers)

Subsystem:
- Read UART data from peripheral block
- Parse protocol
- Update command registers

Example 3: Hardware Timer Periodic Interrupt

// Custom periodic task independent of base rate

Configuration:
   Interruption: 'User Timer1'  (created by peripheral block)
   Triggered_Sub_TimeSource: 'is derived from a hardware timer'
   TIMER_Resolution: 'Resol: 32us - MaxPer: 2.1s'  (prescaler 256)
   IntPriority: 5

Result:
- Dedicated timer allocated automatically
- Interrupt triggers at specified rate
- Independent of Simulink sample times

Example 4: QEI Position Overflow Event

// Extend encoder range with software counter

Configuration:
   Interruption: 'QEI1 - Position Counter Overflow'
   Triggered_Sub_TimeSource: 'is derived from model base rate'
   IntPriority: 6  (high - timing critical)

Subsystem Logic:
if (QEI_DIR == FORWARD)
    ExtendedPosition += 65536;
else
    ExtendedPosition -= 65536;
end

Troubleshooting

        Keep ISR execution time short - long ISRs can cause overload
        Higher priority ISRs can preempt lower priority - ensure reentrancy
        Hardware timer mode consumes one timer resource
        StartupExecute useful for initializing communication protocols

Related Blocks

• MCHP_Scheduler_Options - Multitasking scheduler configuration
• MCHP_Master - Clock and device configuration
• MCHP_ADC_Universal - ADC interrupt sources
• MCHP_PWM_HS_FEP - PWM event interrupts