Inputs: None (configuration block only)
Outputs: None (configuration block only)
This is the master configuration block that defines target device and system settings. It does not have signal portsβit provides global configuration used by all other MCHP blocks in the model.
The Master block supports 800+ Microchip microcontrollers across multiple families:
| Family | Examples | Features | Applications |
|---|---|---|---|
| dsPIC30F | 30F1010, 30F2020, 30F6015 | Legacy DSC, basic DSP engine | Motor control, power supplies |
| dsPIC33F | 33FJ128MC802, 33FJ256GP710A | Enhanced DSP, DMA, advanced PWM | Digital power, motor control |
| dsPIC33E | 33EP512MU810, 33EP256MC710 | PPS, DMA, high-speed ADC | Motor control, instrumentation |
| dsPIC33C | 33CK64MC105, 33CH128MP508 | Dual-core options, high-speed PWM | Motor control, power conversion |
| dsPIC33A | (Latest) | 33AK128MC106, 33AK512MPS512 | Advanced PWM with FEP, 12-bit ADC |
| PIC24F/H | 24F16KL402, 24FJ256GB110 | General-purpose MCU, low power | Portable, battery-powered apps |
| Family | Examples | Features | Applications |
|---|---|---|---|
| PIC32MK | 32MK0512MCF064, 32MK1024GPE100 | MIPS M5150, FPU, motor control | Advanced motor control |
| PIC32MZ | 32MZ2048EFM144, 32MZ1024ECH144 | High-performance MIPS, crypto | IoT, connectivity, graphics |
| PIC32MX | 32MX795F512L, 32MX440F256H | USB, Ethernet, graphics | HMI, connectivity |
| PIC32A | (New) | 32AK1216GC41036 | Next-gen 32-bit architecture |
| Family | Core | Examples | Features |
|---|---|---|---|
| SAME70 | Cortex-M7 | SAME70Q21B, SAME70N21B | 300 MHz, FPU, DSP, Ethernet |
| SAMS70 | Cortex-M7 | SAMS70Q21B | High-speed processing, security |
| SAMV71 | Cortex-M7 | SAMV71Q21B | Automotive, CAN-FD, safety |
| SAME5x | Cortex-M4F | SAME54P20A | 120 MHz, crypto, low power |
| SAMC2x | Cortex-M0+ | SAMC21N18A | Motor control, cost-optimized |
| SAMD2x | Cortex-M0+ | SAMD21G18A | Ultra-low power, IoT |
| PIC32CZ | Cortex-M7 | PIC32CZ_MC70 | High-performance, security |
| Parameter | Description | Values/Range |
|---|---|---|
| PICREF | Microcontroller selection. Dynamic popup filtered by supported families with oscillator support verification. | 800+ devices |
| PACKAGE | (SAM only) | Package selection for ARM devices (affects pin availability). |
| Parameter | Description | Values/Range |
|---|---|---|
| OSCILLATOR_SELECT | Primary oscillator source selection. Options dynamically updated based on chip capabilities. | β’ Internal Fast RC (FRC) |
| QUARTZ | Crystal/resonator frequency when using external oscillator. | 0.4 MHz to 40 MHz |
| ACTIV_PLL | Enable Phase-Locked Loop for frequency multiplication. | on / off |
| MIPS_DESIRED | Target instruction cycle frequency (FCY). Automatically calculates PLL settings. | Device-specific |
| ACLKCON | (dsPIC33C only) | Auxiliary clock configuration for PWM and other peripherals. |
| CPUDIV | (SAM Cortex-M0+ only) | CPU clock divider selection. |
| VDD_range | (SAM Cortex-M0+ only) | Operating voltage range (affects flash wait states). |
Select oscillator source (internal RC or external crystal/clock)
If using crystal, specify frequency in QUARTZ parameter
Enable PLL if higher frequencies are required
Set MIPS_DESIRED to target frequency - PLL multipliers are calculated automatically
Block display shows achieved MIPS/MHz on the diagram
The Master block exposes device-specific configuration fuses extracted from Microchip XML specifications. Available fuses depend on the selected chip.
| Common Fuse Categories | Examples | Description |
|---|---|---|
| Watchdog Timer | FWDTEN, FWDTPS | Watchdog enable and prescaler settings |
| Code Protection | FCPS, FBOR | Read/write protection, boot segment protection |
| Debugging | FICD, FJTAG | ICD/JTAG enable, pin selection |
| Power Management | FBOR, FPOR | Brown-out reset, power-on reset settings |
| Peripheral Config | FIOEN, FBS | Peripheral pin select, boot segment |
| Parameter | Description | Notes |
|---|---|---|
| Master/Slave Selection | For dsPIC33CH dual-core devices, select chip name ending with “S1” for slave core configuration. | β’ Master: 33CH128MP508 |
| SECONDARYIMAGE | Automatically set to slave image name when slave device is selected. | Used by build system to link secondary core code |
| Parameter | Description | Set By |
|---|---|---|
| Compiler Path | Automatically detected compiler installation paths. | Auto-configured from system |
| Header Paths | Include directories for device headers. | Auto-configured from DFP |
| Linker Script | Memory map linker script selection. | Auto-selected or custom |
| Library Paths | Standard library paths (math, DSP, etc.). | Auto-configured |
| Parameter | Description | Values |
|---|---|---|
| UART Selection | UART peripheral for external mode communication. | UART1-4 (device-dependent) |
| Baud Rate | Communication speed for real-time monitoring. | 9600 to 921600 bps |
| Buffer Size | Communication buffer allocation. | 256 to 4096 bytes |
| Parameter | Description | Usage |
|---|---|---|
| BUSYFLAG | Assign a GPIO pin to toggle during task execution for timing analysis. | β’ Not used |
The Master block creates essential variables in the model workspace (accessible to all blocks):
| Variable | Description | Example |
|---|---|---|
| MCHP.id.name | Selected chip reference | ‘33AK128MC106’ |
| MCHP.id.Arch | Architecture ID | 8 (dsPIC33A), 5 (SAM M7) |
| MCHP.fcy.FCY | Instruction cycle frequency (Hz) | 100e6 (100 MIPS) |
| MCHP.fcy.FOSC | Oscillator frequency (Hz) | 200e6 (200 MHz) |
| MCHP.NTIMERS | Number of available timers | 1-12 (device-dependent) |
| MCHP.modsrc.* | Peripheral availability flags | DOS module indicators |
| MCHP.Rx | Pin remapping (PPS) data structure | Available remappable pins |
The Master block automatically configures critical code generation parameters:
RTWSystemTargetFile to appropriate .tlc file% Select dsPIC33AK128MC106
% Configure for motor control application
PICREF: 33AK128MC106
OSCILLATOR_SELECT: Crystal / Ceramic resonator
QUARTZ: 8e6 % 8 MHz crystal
ACTIV_PLL: on % Enable PLL
MIPS_DESIRED: 100e6 % 100 MIPS target
% Result: FCY = 100 MHz, FOSC = 200 MHz
% PLL automatically configured: M=50, N1=2, N2=2
% Select SAME70Q21B with LQFP package
% High-performance application
PICREF: SAME70Q21B - LQFP144
OSCILLATOR_SELECT: Crystal Oscillator
QUARTZ: 12e6 % 12 MHz crystal
ACTIV_PLL: on % Enable PLL
MIPS_DESIRED: 300e6 % 300 MHz ARM core
% Result: MCLK = 300 MHz
% Master core configuration
% Slave core built separately
PICREF: 33CH128MP508 % Master core
OSCILLATOR_SELECT: Internal Fast RC (FRC)
ACTIV_PLL: on
MIPS_DESIRED: 90e6 % 90 MIPS master
% Slave project uses: 33CH128MP508S1
% Ultra-low power IoT application
PICREF: SAMD21G18A
OSCILLATOR_SELECT: Internal 48MHz Oscillator
ACTIV_PLL: off
CPUDIV: 1 % No division
VDD_range: 2.7V to 3.6V % Standard voltage
% Result: 48 MHz operation
Configure UART in Master block for external mode
Set baud rate (typically 115200 or higher)
In Simulink Configuration Parameters:
Code Generation β Interface β External mode
Set transport to “tcpip” or “serial”
Build and download code to target
Connect via Simulink External Mode toolbar
Monitor/tune parameters in real-time
| Problem | Cause | Solution |
|---|---|---|
| Block GUI closes on Apply | Normal behavior when changing devices (fuse structure changes) | Re-open block to see updated configuration |
| Compiler not found | XC16/XC32 not installed or not in PATH | Install compiler from Microchip website, run picSetup |
| Desired MIPS not achievable | PLL limitations or oscillator range | Check datasheet for valid PLL settings, try different crystal |
| Fuses not visible | Device XML not found or old blockset version | Ensure DFP installed, update blockset |
| Code generation fails | Missing DFP or linker script | Check compiler optimization block, verify DFP installation |
The Master block MUST be present before adding any other MCHP blocks
Changing the target device may invalidate peripheral block configurations
Always verify achieved MIPS matches application requirements
Dual-core devices require separate projects for master and slave cores
External mode requires dedicated UART - cannot be shared with application