Master Block Icon
CRITICAL: The Master block is MANDATORY in every MCHP Blockset model. This is always the FIRST block to add to any new model. Without it, no other MCHP blocks will function. The Master block is the central configuration block for the entire MCHP Blockset. It defines the target microcontroller, clock configuration, peripheral initialization, compiler settings, and code generation options.

Block Inputs/Outputs

Inputs: None (configuration block only)

Outputs: None (configuration block only)

This is the master configuration block that defines target device and system settings. It does not have signal portsβ€”it provides global configuration used by all other MCHP blocks in the model.

Supported Devices

The Master block supports 800+ Microchip microcontrollers across multiple families:

16-bit DSC/MCU Families

FamilyExamplesFeaturesApplications
dsPIC30F30F1010, 30F2020, 30F6015Legacy DSC, basic DSP engineMotor control, power supplies
dsPIC33F33FJ128MC802, 33FJ256GP710AEnhanced DSP, DMA, advanced PWMDigital power, motor control
dsPIC33E33EP512MU810, 33EP256MC710PPS, DMA, high-speed ADCMotor control, instrumentation
dsPIC33C33CK64MC105, 33CH128MP508Dual-core options, high-speed PWMMotor control, power conversion
dsPIC33A(Latest)33AK128MC106, 33AK512MPS512Advanced PWM with FEP, 12-bit ADC
PIC24F/H24F16KL402, 24FJ256GB110General-purpose MCU, low powerPortable, battery-powered apps

32-bit MCU Families

FamilyExamplesFeaturesApplications
PIC32MK32MK0512MCF064, 32MK1024GPE100MIPS M5150, FPU, motor controlAdvanced motor control
PIC32MZ32MZ2048EFM144, 32MZ1024ECH144High-performance MIPS, cryptoIoT, connectivity, graphics
PIC32MX32MX795F512L, 32MX440F256HUSB, Ethernet, graphicsHMI, connectivity
PIC32A(New)32AK1216GC41036Next-gen 32-bit architecture

ARM-based Families (SAM)

FamilyCoreExamplesFeatures
SAME70Cortex-M7SAME70Q21B, SAME70N21B300 MHz, FPU, DSP, Ethernet
SAMS70Cortex-M7SAMS70Q21BHigh-speed processing, security
SAMV71Cortex-M7SAMV71Q21BAutomotive, CAN-FD, safety
SAME5xCortex-M4FSAME54P20A120 MHz, crypto, low power
SAMC2xCortex-M0+SAMC21N18AMotor control, cost-optimized
SAMD2xCortex-M0+SAMD21G18AUltra-low power, IoT
PIC32CZCortex-M7PIC32CZ_MC70High-performance, security

Block Parameters

Target Configuration

ParameterDescriptionValues/Range
PICREFMicrocontroller selection. Dynamic popup filtered by supported families with oscillator support verification.800+ devices
PACKAGE(SAM only)Package selection for ARM devices (affects pin availability).

Clock Configuration

ParameterDescriptionValues/Range
OSCILLATOR_SELECTPrimary oscillator source selection. Options dynamically updated based on chip capabilities.β€’ Internal Fast RC (FRC)
QUARTZCrystal/resonator frequency when using external oscillator.0.4 MHz to 40 MHz
ACTIV_PLLEnable Phase-Locked Loop for frequency multiplication.on / off
MIPS_DESIREDTarget instruction cycle frequency (FCY). Automatically calculates PLL settings.Device-specific
ACLKCON(dsPIC33C only)Auxiliary clock configuration for PWM and other peripherals.
CPUDIV(SAM Cortex-M0+ only)CPU clock divider selection.
VDD_range(SAM Cortex-M0+ only)Operating voltage range (affects flash wait states).
        Select oscillator source (internal RC or external crystal/clock)
        If using crystal, specify frequency in QUARTZ parameter
        Enable PLL if higher frequencies are required
        Set MIPS_DESIRED to target frequency - PLL multipliers are calculated automatically
        Block display shows achieved MIPS/MHz on the diagram

Fuse Configuration (Device Configuration Bits)

The Master block exposes device-specific configuration fuses extracted from Microchip XML specifications. Available fuses depend on the selected chip.

Common Fuse CategoriesExamplesDescription
Watchdog TimerFWDTEN, FWDTPSWatchdog enable and prescaler settings
Code ProtectionFCPS, FBORRead/write protection, boot segment protection
DebuggingFICD, FJTAGICD/JTAG enable, pin selection
Power ManagementFBOR, FPORBrown-out reset, power-on reset settings
Peripheral ConfigFIOEN, FBSPeripheral pin select, boot segment

Dual-Core Configuration (dsPIC33CH only)

ParameterDescriptionNotes
Master/Slave SelectionFor dsPIC33CH dual-core devices, select chip name ending with “S1” for slave core configuration.β€’ Master: 33CH128MP508
SECONDARYIMAGEAutomatically set to slave image name when slave device is selected.Used by build system to link secondary core code

Build Configuration

ParameterDescriptionSet By
Compiler PathAutomatically detected compiler installation paths.Auto-configured from system
Header PathsInclude directories for device headers.Auto-configured from DFP
Linker ScriptMemory map linker script selection.Auto-selected or custom
Library PathsStandard library paths (math, DSP, etc.).Auto-configured

External Mode Configuration

ParameterDescriptionValues
UART SelectionUART peripheral for external mode communication.UART1-4 (device-dependent)
Baud RateCommunication speed for real-time monitoring.9600 to 921600 bps
Buffer SizeCommunication buffer allocation.256 to 4096 bytes

Busy Flag (Debug Output)

ParameterDescriptionUsage
BUSYFLAGAssign a GPIO pin to toggle during task execution for timing analysis.β€’ Not used

Generated Model Workspace Variables

The Master block creates essential variables in the model workspace (accessible to all blocks):

VariableDescriptionExample
MCHP.id.nameSelected chip reference‘33AK128MC106’
MCHP.id.ArchArchitecture ID8 (dsPIC33A), 5 (SAM M7)
MCHP.fcy.FCYInstruction cycle frequency (Hz)100e6 (100 MIPS)
MCHP.fcy.FOSCOscillator frequency (Hz)200e6 (200 MHz)
MCHP.NTIMERSNumber of available timers1-12 (device-dependent)
MCHP.modsrc.*Peripheral availability flagsDOS module indicators
MCHP.RxPin remapping (PPS) data structureAvailable remappable pins

Code Generation Settings

The Master block automatically configures critical code generation parameters:

  • Target Selection: Sets RTWSystemTargetFile to appropriate .tlc file
  • Compiler Detection: Automatically finds and configures XC16/XC32/XC-DSC compiler paths
  • DFP Integration: Loads Device Family Pack for accurate peripheral definitions
  • PPS Configuration: Enables Peripheral Pin Select for remappable devices
  • Code Replacement: Optionally enables optimized DSP assembly libraries

Examples

Example 1: Basic dsPIC33A Configuration

% Select dsPIC33AK128MC106
% Configure for motor control application

PICREF: 33AK128MC106
OSCILLATOR_SELECT: Crystal / Ceramic resonator
QUARTZ: 8e6              % 8 MHz crystal
ACTIV_PLL: on            % Enable PLL
MIPS_DESIRED: 100e6      % 100 MIPS target

% Result: FCY = 100 MHz, FOSC = 200 MHz
% PLL automatically configured: M=50, N1=2, N2=2

Example 2: SAME70 ARM Cortex-M7 Setup

% Select SAME70Q21B with LQFP package
% High-performance application

PICREF: SAME70Q21B - LQFP144
OSCILLATOR_SELECT: Crystal Oscillator
QUARTZ: 12e6             % 12 MHz crystal
ACTIV_PLL: on            % Enable PLL
MIPS_DESIRED: 300e6      % 300 MHz ARM core

% Result: MCLK = 300 MHz

Example 3: dsPIC33CH Dual-Core Master

% Master core configuration
% Slave core built separately

PICREF: 33CH128MP508     % Master core
OSCILLATOR_SELECT: Internal Fast RC (FRC)
ACTIV_PLL: on
MIPS_DESIRED: 90e6       % 90 MIPS master

% Slave project uses: 33CH128MP508S1

Example 4: Low-Power SAMD21 Configuration

% Ultra-low power IoT application

PICREF: SAMD21G18A
OSCILLATOR_SELECT: Internal 48MHz Oscillator
ACTIV_PLL: off
CPUDIV: 1                % No division
VDD_range: 2.7V to 3.6V  % Standard voltage

% Result: 48 MHz operation

Common Workflows

New Model Setup

  • Create new Simulink model
  • Open MCHP Blockset library
  • Drag Master block to model (FIRST block)
  • Double-click Master block to open configuration dialog
  • Select target microcontroller from PICREF dropdown
  • Configure clock settings for desired frequency
  • Set any required fuse configuration bits
  • Click OK/Apply - block display shows chip name and achieved MIPS
  • Add other MCHP peripheral blocks as needed

Changing Target Device

  • Open Master block
  • Select new device from PICREF dropdown
  • Click Apply - GUI closes automatically due to parameter structure change
  • Re-open Master block - new fuses and clock options now visible
  • Reconfigure clock and fuses for new device
  • Review all peripheral blocks for compatibility warnings

External Mode Setup

  • Configure UART in Master block for external mode

  • Set baud rate (typically 115200 or higher)

  • In Simulink Configuration Parameters:

  • Code Generation β†’ Interface β†’ External mode

  • Set transport to “tcpip” or “serial”

  • Build and download code to target

  • Connect via Simulink External Mode toolbar

  • Monitor/tune parameters in real-time

Troubleshooting

Common Issues

ProblemCauseSolution
Block GUI closes on ApplyNormal behavior when changing devices (fuse structure changes)Re-open block to see updated configuration
Compiler not foundXC16/XC32 not installed or not in PATHInstall compiler from Microchip website, run picSetup
Desired MIPS not achievablePLL limitations or oscillator rangeCheck datasheet for valid PLL settings, try different crystal
Fuses not visibleDevice XML not found or old blockset versionEnsure DFP installed, update blockset
Code generation failsMissing DFP or linker scriptCheck compiler optimization block, verify DFP installation
        The Master block MUST be present before adding any other MCHP blocks
        Changing the target device may invalidate peripheral block configurations
        Always verify achieved MIPS matches application requirements
        Dual-core devices require separate projects for master and slave cores
        External mode requires dedicated UART - cannot be shared with application

See Also

Other