Master

dsPIC30F dsPIC33F dsPIC33E dsPIC33C dsPIC33A PIC32

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CRITICAL: The Master block is MANDATORY in every MCHP Blockset model. This is always the FIRST block to add to any new model. Without it, no other MCHP blocks will function. The Master block is the central configuration block for the entire MCHP Blockset. It defines the target microcontroller, clock configuration, peripheral initialization, compiler settings, and code generation options.

When to use:

When to use:

• Starting ANY new MCHP Blockset model (MANDATORY — always first block)
• Changing target microcontroller or development board
• Configuring system clock frequency (crystal, PLL, internal RC)
• Setting device configuration bits (watchdog, code protection, debug pins)

When NOT to use:

• Understanding that this block is REQUIRED in every model — no exceptions
• Selecting a supported device family (800+ dsPIC/PIC32/SAM chips available)
• Verifying clock configuration achieves desired MIPS/MHz for application timing

Block Dialog

Oscillator Tab

Memory Tab

Debug Tab

Dual Core Tab

Ports

Inputs: None (configuration block only)

Outputs: None (configuration block only)

This is the master configuration block that defines target device and system settings. It does not have signal ports—it provides global configuration used by all other MCHP blocks in the model.

Parameters

Target Configuration

Clock Configuration

        Select oscillator source (internal RC or external crystal/clock)
        If using crystal, specify frequency in QUARTZ parameter
        Enable PLL if higher frequencies are required
        Set MIPS_DESIRED to target frequency - PLL multipliers are calculated automatically
        Block display shows achieved MIPS/MHz on the diagram

FRC / BFRC Tuning

Scope — dsPIC33F, dsPIC33E, dsPIC33C (CK / CH) and dsPIC33A only. Ignored on chips without an OSCTUN register.

The internal Fast RC oscillator (FRC) and, on dsPIC33A, the Backup FRC (BFRC) can be trimmed at run-time through the OSCTUN register. The Master block exposes this as a popup built from the chip’s datasheet grid, plus a Custom entry that accepts a MATLAB expression evaluated against the base workspace.

Register encoding — The Master block converts the selected percentage into a signed 6-bit value written to OSCTUN.TUN (FRC) or OSCTUN.BTUN (BFRC, dsPIC33A only):

• Positive percent: TUN = round(pct / max_pos × 31) → range 0 … +31
• Negative percent: TUN = −round(|pct| / max_neg × 32) → range −32 … −1

The conversion is handled by MCHP_Master_OscTuneToRegister. max_pos / max_neg per grid: Range12_Step0P375 → (11.625, 12.0); Range1P5_Step0P047 → (1.45, 1.5).

Custom expression — Selecting Custom in the popup enables a sibling edit field (*_CUSTOM) that accepts any numeric MATLAB expression (including workspace variables). The expression is evaluated at build time, clamped to the grid range, and quantised to the nearest 6-bit step before being written to the register. Use this to pass calibration data loaded from, for example, a factory-test routine:

load('factory_calibration.mat', 'frcTrimPct');   % e.g. +0.235
set_param([mdl '/Master'], 'FRC_TUNE_Range1P5_Step0P047', 'Custom');
set_param([mdl '/Master'], 'FRC_TUNE_Range1P5_Step0P047_CUSTOM', 'frcTrimPct');

When to use — Temperature compensation of FRC-driven clocks, factory trim-to-target, characterising an unknown FRC drift before moving to a crystal, or deriving a calibrated baud-rate from an uncharacterised device.

Limitations — FRC / BFRC tuning does not compensate for long-term drift; for applications that require < 1 % frequency accuracy, use an external crystal or ceramic resonator via the Crystal/Ceramic Resonator oscillator source.

Fuse Configuration (Device Configuration Bits)

The Master block exposes device-specific configuration fuses extracted from Microchip XML specifications. Available fuses depend on the selected chip.

Dual-Core Configuration (dsPIC33CH only)

Build Configuration

External Mode Configuration

Busy Flag (Debug Output)

16-bit DSC/MCU Families

32-bit MCU Families

ARM-based Families (SAM)

Generated Model Workspace Variables

The Master block creates essential variables in the model workspace (accessible to all blocks):

Code Generation Settings

The Master block automatically configures critical code generation parameters:

• Target Selection: Sets RTWSystemTargetFile to appropriate .tlc file
• Compiler Detection: Automatically finds and configures XC16/XC32/XC-DSC compiler paths
• DFP Integration: Loads Device Family Pack for accurate peripheral definitions
• PPS Configuration: Enables Peripheral Pin Select for remappable devices
• Code Replacement: Optionally enables optimized DSP assembly libraries

Common Workflows

New Model Setup

• Create new Simulink model
• Open MCHP Blockset library
• Drag Master block to model (FIRST block)
• Double-click Master block to open configuration dialog
• Select target microcontroller from PICREF dropdown
• Configure clock settings for desired frequency
• Set any required fuse configuration bits
• Click OK/Apply - block display shows chip name and achieved MIPS
• Add other MCHP peripheral blocks as needed

Changing Target Device

• Open Master block
• Select new device from PICREF dropdown
• Click Apply - GUI closes automatically due to parameter structure change
• Re-open Master block - new fuses and clock options now visible
• Reconfigure clock and fuses for new device
• Review all peripheral blocks for compatibility warnings

External Mode Setup

• Configure UART in Master block for external mode

• Set baud rate (typically 115200 or higher)

• In Simulink Configuration Parameters:

• Code Generation → Interface → External mode

• Set transport to “tcpip” or “serial”

• Build and download code to target

• Connect via Simulink External Mode toolbar

• Monitor/tune parameters in real-time

Device Support

The Master block supports 800+ Microchip microcontrollers across multiple families:

Examples

Programmatic Setup

% Add block to model
add_block('MCHP_Blockset/System Configuration/Microchip Master', [mdl '/Master']);

% Configure key parameters
set_param([mdl '/Master'], 'PICREF', '33CK64MC105');
set_param([mdl '/Master'], 'OSCILLATOR_SELECT', 'Internal Fast RC (FRC)');
set_param([mdl '/Master'], 'ACTIV_PLL', 'on');
set_param([mdl '/Master'], 'MIPS_DESIRED', '100e6');

Example 1: Basic dsPIC33A Configuration

% Select dsPIC33AK128MC106
% Configure for motor control application

PICREF: 33AK128MC106
OSCILLATOR_SELECT: Crystal / Ceramic resonator
QUARTZ: 8e6              % 8 MHz crystal
ACTIV_PLL: on            % Enable PLL
MIPS_DESIRED: 100e6      % 100 MIPS target

% Result: FCY = 100 MHz, FOSC = 200 MHz
% PLL automatically configured: M=50, N1=2, N2=2

Example 2: SAME70 ARM Cortex-M7 Setup

% Select SAME70Q21B with LQFP package
% High-performance application

PICREF: SAME70Q21B - LQFP144
OSCILLATOR_SELECT: Crystal Oscillator
QUARTZ: 12e6             % 12 MHz crystal
ACTIV_PLL: on            % Enable PLL
MIPS_DESIRED: 300e6      % 300 MHz ARM core

% Result: MCLK = 300 MHz

Example 3: dsPIC33CH Dual-Core Master

% Master core configuration
% Slave core built separately

PICREF: 33CH128MP508     % Master core
OSCILLATOR_SELECT: Internal Fast RC (FRC)
ACTIV_PLL: on
MIPS_DESIRED: 90e6       % 90 MIPS master

% Slave project uses: 33CH128MP508S1

Example 4: Low-Power SAMD21 Configuration

% Ultra-low power IoT application

PICREF: SAMD21G18A
OSCILLATOR_SELECT: Internal 48MHz Oscillator
ACTIV_PLL: off
CPUDIV: 1                % No division
VDD_range: 2.7V to 3.6V  % Standard voltage

% Result: 48 MHz operation

Troubleshooting

Common Issues

        The Master block MUST be present before adding any other MCHP blocks
        Changing the target device may invalidate peripheral block configurations
        Always verify achieved MIPS matches application requirements
        Dual-core devices require separate projects for master and slave cores
        External mode requires dedicated UART - cannot be shared with application

References

• Microchip Motor Control