The MSI block configures the Master Secondary Interface (MSI) for inter-core communication in dual-core dsPIC33CH devices, enabling data exchange between master and secondary cores.
Communication Methods
| Method | Speed | Size | Direction | Use Case |
|---|
| Mailboxes | Fast | 16 words × 16 boxes | Bidirectional | Control parameters, flags |
| FIFO | Medium | Configurable buffer | Bidirectional | Data streaming, logs |
| Protocol Interrupts | Immediate | N/A | Bidirectional | Event notification, sync |
Block Parameters
| Parameter | Description | Options |
|---|
| Communication Type | Select MSI communication method | Mailbox / FIFO / Protocol Interrupt |
| Mailbox Number | Mailbox index (0-15) | 0 to 15 |
| Direction | Data transfer direction | Master→Secondary |
| FIFO Size | FIFO buffer size | 16 to 256 words |
| Interrupt Enable | Generate interrupt on data available | on / off |
Example Dual-Core Communication
% Master Core (33CH128MP508):
MSI_Mailbox0_Write:
- Write speed reference to Mailbox 0
- Trigger secondary interrupt
MSI_Mailbox1_Read:
- Read current measurement from Mailbox 1
- Update speed controller
% Secondary Core (33CH128MP508S1):
MSI_Mailbox0_Read:
- Read speed reference from Mailbox 0
- Execute in interrupt handler
MSI_Mailbox1_Write:
- Write current measurement to Mailbox 1
- Trigger master interrupt
Mailbox vs FIFO Selection
| Scenario | Recommended | Reason |
|---|
| Control loop parameters | Mailbox | Fast, deterministic, 16 words enough |
| Sensor data streaming | FIFO | Buffered, handles variable rates |
| Event flags, status | Mailbox | Immediate, small data |
| Data logging | FIFO | Large buffer, non-critical timing |
| Synchronization signals | Protocol Interrupt | No data, just notification |
Synchronization Example
% Master triggers secondary task execution
Master:
compute_reference();
MSI_SendProtocolInterrupt(SECONDARY_START);
Secondary (Interrupt Handler):
if (protocol_interrupt == SECONDARY_START)
execute_fast_control_loop();
MSI_SendProtocolInterrupt(TASK_COMPLETE);
end
% Result: Precise task synchronization between cores
See Also
- [MCHP_SECONDARY_CORE] - Secondary core configuration
- [MCHP_Master] - Dual-core device selection
