MSI
When to use:
When to use:
- dsPIC33CH dual-core device (master-slave architecture)
- Inter-core communication needed (master ↔ slave data exchange)
- Load balancing across two cores (main handles control, slave handles real-time PWM)
- Mailbox-based synchronization required (hardware-accelerated, zero-copy transfer)
- Protocol interrupts for core-to-core event signaling
When NOT to use:
- Single-core device — MSI peripheral not available
- No need for inter-core communication — use standard peripherals instead
- External communication required — use UART/CAN/SPI for off-chip data
- Simple GPIO signaling suffices — MSI adds complexity for trivial cases
Overview
The MAIN-SECONDARY INTERFACE (MSI) block enables data exchange between the master and secondary cores in dsPIC33CH dual-core devices. The MSI peripheral provides hardware-accelerated mailbox communication with protocol synchronization, allowing efficient inter-core data transfer without CPU polling overhead.
Key Features
- Mailbox-based data transfer with up to 16 mailboxes (16 words each)
- Protocol-based synchronization with 8 independent protocol channels (A-H)
- Supports up to 32 data items per block with mixed data types
- Automatic mailbox allocation and management
- Bidirectional communication (master ↔ secondary)
- Zero-copy data exchange via shared memory
Typical Use Cases
- Motor Control: Main core computes reference values, secondary core executes real-time PWM control
- Sensor Fusion: Main core processes sensor data, secondary core handles high-speed acquisition
- Load Balancing: Distribute computational tasks across both cores
- Real-Time Communication: Main core manages communication protocols, secondary core handles time-critical tasks
Parameters
| Parameter | Description | Options | Variable |
|---|---|---|---|
| direction | Data transfer direction | send to main core / receive from main core / send to secondary core / receive from secondary core | direction |
| Offset | Starting mailbox number for data allocation | 0 to 15 | Offset |
| protocol | Protocol channel for synchronization | use protocol A through H | protocol |
| NData | Number of data items to transfer (1-32) | 1 to 32 | NData |
| Data1-Data32 | Data type for each item | unsigned int8/int16/int32, signed int8/int16/int32, single, double | Data1-Data32 |
| SampleTime | Block execution rate | -1 (inherited), or numeric value | SampleTime |
Configuration Workflow
- Set Direction: Choose send/receive and core (main/secondary)
- Select Mailbox Offset: Choose starting mailbox number (prevents conflicts with other MSI blocks)
- Choose Protocol: Select protocol channel A-H for synchronization
- Define Data Count: Set number of data items (1-32)
- Specify Data Types: Configure data type for each item
Important: MSI blocks on master and secondary cores must have matching configurations. Drag and drop the block from master to secondary model to ensure consistency.
Example Dual-Core Communication
% Master Core (33CH128MP508):
MSI_Mailbox0_Write:
- Write speed reference to Mailbox 0
- Trigger secondary interrupt
MSI_Mailbox1_Read:
- Read current measurement from Mailbox 1
- Update speed controller
% Secondary Core (33CH128MP508S1):
MSI_Mailbox0_Read:
- Read speed reference from Mailbox 0
- Execute in interrupt handler
MSI_Mailbox1_Write:
- Write current measurement to Mailbox 1
- Trigger master interrupt
Mailbox vs FIFO Selection
| Scenario | Recommended | Reason |
|---|---|---|
| Control loop parameters | Mailbox | Fast, deterministic, 16 words enough |
| Sensor data streaming | FIFO | Buffered, handles variable rates |
| Event flags, status | Mailbox | Immediate, small data |
| Data logging | FIFO | Large buffer, non-critical timing |
| Synchronization signals | Protocol Interrupt | No data, just notification |
Synchronization Example
% Master triggers secondary task execution
Master:
compute_reference();
MSI_SendProtocolInterrupt(SECONDARY_START);
Secondary (Interrupt Handler):
if (protocol_interrupt == SECONDARY_START)
execute_fast_control_loop();
MSI_SendProtocolInterrupt(TASK_COMPLETE);
end
% Result: Precise task synchronization between cores
Related Blocks
- Secondary Core — Secondary core configuration
- Master — Dual-core device selection