Register Access
When to use:
- Tweaking a peripheral register that the standard blocks do not expose (advanced feature, errata work-around, experimental peripheral).
- Reading silicon-specific status or calibration registers during development.
- Custom peripheral bring-up before a dedicated block exists in the library.
- Run-time parameter tuning where a scalar input needs to map directly onto a hardware bit-field.
When NOT to use:
- A dedicated block already exists for the peripheral (use it — the dedicated block handles PPS routing, interrupt declaration, clock dependencies, etc., which Register Access does not).
- Writing to registers that are already owned by another MCHP block in the same model (conflicts are not detected by this block).
- Safety-critical outputs without explicit Saturation on the inputs — Register Access performs no range checking.
Block Dialog
The Register Access block opens a dedicated configuration GUI (launched by double-click) with three tabs — Init, Write, Read — and a set of global options.
| Section | Direction | When code runs | Simulink ports |
|---|---|---|---|
| Init | Constant → Register | Once, at model start-up | None |
| Write | Input → Register | On every evaluation (or on trigger) | One input per entry |
| Read | Register → Output | On every evaluation (or on trigger) | One output per entry |
Each row is a register or a bit-field entry (notation REGNAME or REGNAME.BITFIELD), a data-type (boolean, uint8, uint16, uint32, float, double), and an optional input / output range for scaled float↔integer conversion.
A FLUSH marker can be inserted between rows of the Init or Write section to force the write to be emitted before the next row (useful when the hardware requires a specific write order or a settling delay). An optional per-FLUSH delay (in clock cycles) is supported.
Parameters
Global Options
| Parameter | Description |
|---|---|
| Chip | Target device (inherited from the Master block; a 16-bit / 32-bit architecture flag is auto-detected and used to size register masks). |
| Trigger Mode | None (every step), Level (while trigger input is high), Rising / Falling / Any Edge. A trigger mode other than None adds one boolean input port at index 0 to the block. |
| Write Atomic (DISI) | When enabled, the generated code wraps the Write section in a DISI / __builtin_disi() critical section so multi-register writes cannot be interrupted. Single-bit operations are automatically optimized to atomic BSET / BCLR instructions and do not need this option. |
| Init Atomic (DISI) | Same as above for the one-shot Init section. |
Entry Columns
| Column | Description |
|---|---|
| Register / Bitfield | REGNAME writes the whole register; REGNAME.BITFIELD writes only the specified field (mask and shift are computed automatically from the chip’s register database). |
| Direction | Write (from Simulink input), Read (to Simulink output) or Init (constant). A Write entry with a Literal value produces a constant write with no Simulink port. |
| Data Type | boolean (1 bit), uint8, uint16, uint32, float, double. float and double enable the scaled conversion described below. |
| Input / Output Range | [min max] range applied to float/double entries. Gain is computed as (2^bits − 1) / (max − min) so the physical quantity at the block port maps linearly onto the register value. |
| Bit-width override | Optional explicit width; by default the width is read from the chip register database. |
| Value (Init / Literal only) | Decimal, hex (0xFF), binary (0b1010), an enumeration name from the register database (e.g. 'Primary' for CLKSEL), or a MATLAB workspace variable name. |
Advanced Options
| Parameter | Description |
|---|---|
| FLUSH marker | Inserted between rows of the Init or Write section. Optional delay in clock cycles to allow peripheral settling. |
| Group union structure on top of the code | Aggregates consecutive writes to the same register into one grouped structure at the top of the generated code (improves readability and often the generated assembly). |
| Flush GUI | GUI action that re-loads the register list from the current chip (useful after changing the Master block chip). |
| Delay option | Insert a cycle-count delay between entries without needing a separate FLUSH row. |
Programmatic API
The block can be configured without opening the GUI through the MCHP_Register_API helper class. A minimal example:
cfg = MCHP_Register_API('dsPIC33CK256MP508'); % Create config for target chip
cfg.addInit('PG1CON.ON', '1'); % Enable PWM generator 1 at startup
cfg.addWrite('PG1DC', 'uint16'); % Duty-cycle from Simulink input
cfg.addRead('PG1STAT.FLTACT', 'boolean'); % Fault flag to Simulink output
cfg.applyTo('myModel/MCHP_Register'); % Push config onto the block
Scaled float entries:
cfg.addWrite('PG1DC', 'float', [0 100]); % 0–100 % input → 0–65535 register
cfg.addRead ('ADCBUF0', 'float', [0 3.3]); % 0–4095 register → 0–3.3 V output
See the class help (help MCHP_Register_API) for the complete method list (addWrite, addWriteLiteral, addRead, addInit, insertFlush, setWriteAtomic, setTriggerMode, fromBlock, applyTo).
Safety Notes
The Register Access block is a power-user tool and bypasses the safety checks performed by the dedicated peripheral blocks. Pay particular attention to the following:
- Multi-register atomicity (SAF-004) — Without the Write Atomic option, writes execute sequentially; an interrupt occurring between two writes will see an inconsistent state. Enable Write Atomic for any multi-register write that must be seen as a single event by the rest of the system.
- Input range validation (SAF-001 / SAF-002) — Inverted ranges (
[max min], negative gain) are not validated, and out-of-range inputs are not clamped. Add a Simulink Saturation block in front of each Write input if the application requires clamping. - Architecture mismatch (SAF-010) — Forcing
archBits = 32on a 16-bit chip is not validated. Keep the chip selection in sync with the Master block. - Cross-block conflicts — If another MCHP block (PWM, ADC, UART, …) already writes to the same register or bit-field, the Register Access block will silently overwrite it. Use the Port Info block to audit pin and register assignments.
Integration with the Datasheet Locator
The Register block’s GUI integrates with the Datasheet Locator helper (MCHP_Fun.DataSheetLocator): right-click a register or bit-field row and select Open datasheet to jump straight to the corresponding page of the device datasheet. This uses a Navigator header trick to avoid microchip.com anti-bot protection on automated lookups.
Examples
Live Register Tuning (development aid)
Connect a Simulink Constant or a dashboard Slider to a uint16 Write entry targeting a single bit-field (for example PG1DC) and run the model in External Mode: the register value updates on the hardware as soon as the slider is moved, without rebuilding the firmware.
Reading a Calibration Register
cfg = MCHP_Register_API('dsPIC33AK512MPS506');
cfg.addRead('DEVID', 'uint32');
cfg.addRead('OSCCAL.FRCTUN', 'uint8');
cfg.applyTo('myModel/RegisterRead');
One-Shot Peripheral Bring-Up
cfg = MCHP_Register_API('dsPIC33CK256MP508');
cfg.addInit('REFOCONL.ROSEL', 'Primary'); % enum from register DB
cfg.addInit('REFOCONL.ROSLP', '0');
cfg.insertFlush('init', 2, 10); % 10-cycle settling delay
cfg.addInit('REFOCONL.ROON', '1');
cfg.applyTo('myModel/RefOscBringUp');
Related Blocks
Port Info — visualize pin assignments and detect conflicts before adding Register Access entries that touch PPS-mapped pins.
Doc — one-click access to the device datasheet and family reference manual.
C Function Call — alternative for inline C code that needs more logic than a simple register write.
Master — required; sets the chip that drives register name resolution.
MCHP_Register_API.m— programmatic configuration helper (inblocks/).help MCHP_Register_API— full method reference.