PIL (Processor-in-the-Loop)

☀️ Light

PIL (Processor-in-the-Loop) runs your generated code on the actual target hardware and verifies both its numerical accuracy and its execution timing.

For real-time parameter tuning and live data visualization, see the companion External Mode guide.

Processor-in-the-Loop (PIL) Simulation

What is PIL?

PIL runs your generated code on the actual target hardware and compares the results to a reference simulation. This provides two critical types of verification:

• Numerical Verification: Confirms code generation produces bit-accurate results
• Timing Analysis: Measures actual execution time and resource usage on hardware

        Fixed-point quantization errors
        Compiler optimization side effects
        Hardware-specific behavior
        Performance bottlenecks

PIL Test Model Structure

Figure 1: PIL test model structure. The algorithm under test runs on hardware (PIL block), while a reference model runs in simulation. Results are compared to verify correctness.

Model components:

• Test Inputs: Signal sources (sine waves, steps, ramps)
• PIL Block: Algorithm running on hardware
• Reference Model: Same algorithm in Simulink
• Comparison: Subtract outputs to check for differences
• Assertion: Fail test if error exceeds threshold

PIL Numerical Verification

Figure 2: PIL numerical verification results. Blue line (simulation) vs. Orange line (hardware execution). In this test, the outputs match exactly, confirming code generation accuracy.

What to verify:

• Floating-point algorithms: Should match simulation exactly (within rounding tolerance)
• Fixed-point algorithms: May have quantization differences - verify they’re acceptable
• Lookup tables: Check interpolation accuracy
• State machines: Verify state transitions

PIL Timing Analysis

Figure 3: PIL timing analysis results showing actual execution time on target hardware. Statistics include minimum, maximum, and average execution times in CPU cycles and microseconds.

Timing metrics provided:

PIL Setup Procedure

Step 1: Create PIL Test Model

1. Create new Simulink model
2. Add test signal sources (sine, step, etc.)
3. Add your algorithm as a subsystem or reference model
4. Add reference implementation for comparison
5. Add comparison logic (subtraction + assertion)

Step 2: Configure Subsystem for PIL

1. Right-click subsystem/model block
2. Select "C/C++ Code" → "Build"
3. In build dialog:
   - Set "Build action" to "Software-in-the-Loop (SIL)"
     or "Processor-in-the-Loop (PIL)"
   - Select PIL for hardware testing
4. Choose hardware connection:
   - ICD3/ICD4/ICD5
   - PICkit 3/4/5
   - MPLAB SNAP
5. Click "Build"

Step 3: Run PIL Test

1. Configure PIL from Microchip tab -> Ext-Mode -> PIL settings,
   then run the PIL test model in Simulink (Run button).
2. Code is automatically:
   - Generated
   - Compiled
   - Programmed to hardware
   - Executed with test inputs
3. Results compared to reference
4. Report generated with timing data

Interpreting PIL Results

Numerical Verification Pass Criteria

Timing Analysis Guidelines

Example Timing Report:
  Function: ControlLoop
  Min time:  45 μs  (2,250 cycles @ 50 MHz)
  Max time:  67 μs  (3,350 cycles @ 50 MHz)
  Avg time:  52 μs  (2,600 cycles @ 50 MHz)

Analysis:
  • Sample period: 100 μs (10 kHz control loop)
  • Worst case: 67 μs < 100 μs ✅ PASS
  • CPU load: 52 / 100 = 52% average
  • Safety margin: 100 - 67 = 33 μs (33% margin) ✅ GOOD

** Timing Failure:** If maximum execution time exceeds sample period:

• Optimize code: Use PIL profiling to find bottlenecks
• Enable optimizations: Check compiler settings (-O1/-O2/-O3)
• Use code replacement: Enable assembly optimizations for dsPIC
• Reduce sample rate: Increase sample period if possible
• Upgrade hardware: Consider faster microcontroller

Best Practices

• Test early and often: Run PIL after major algorithm changes
• Use realistic test inputs: Cover full operating range
• Check worst-case timing: Verify maximum execution time
• Test with optimizations: PIL with same settings as production
• Automate PIL tests: Integrate into CI/CD pipeline
• Document results: Keep timing reports for reference

External Mode vs PIL

Workflow Recommendation

Development Phase:
  1. Develop algorithm in Simulink (pure simulation)
  2. Test with PIL for numerical verification
  3. Optimize if timing fails
  4. Deploy to hardware
  5. Use External Mode for tuning
  6. Final PIL test with tuned parameters

Production Phase:
  7. Disable External Mode (remove overhead)
  8. Build production code
  9. Final verification with PIL
  10. Program production units

Troubleshooting

PIL Test Failures

Problem: Numerical mismatch between simulation and hardware

Possible causes:

• Fixed-point quantization: Check word lengths and scaling
• Compiler optimization: May reorder operations (usually safe)
• Uninitialized variables: Hardware vs simulation default values differ
• Timing-dependent logic: Sample time mismatch

Problem: Timing exceeds sample period

Solutions:

• Enable compiler optimizations (-O2 or -O3)
• Enable code replacement library (assembly optimizations)
• Profile code to find bottleneck functions
• Simplify algorithm or increase sample period

Related Documentation

📹 See it in action: PIL (3:05) · All demos →

• External Mode - Real-time parameter tuning and data visualization
• Compiler Optimization Block
• Scheduler & Multitasking Guide

See Also

Quick Start Guide | Board Templates | External Mode | User Guide