Dual-Core (dsPIC33CH)

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The dsPIC33CH family integrates two CPU cores on one device — a Main core and a Secondary core — that run independently and exchange data through the hardware Main-Secondary Interface (MSI). The MPLAB Blockset supports this architecture with two Simulink models (one per core) plus two dedicated blocks.

Dual-core applies only to dsPIC33CH devices. On single-core parts the MSI peripheral is absent and these blocks report not available.

Architecture at a glance

   ┌─────────────── dsPIC33CHxxxMP5xx (one chip) ───────────────┐
   │                                                            │
   │   MAIN core  ◄────── MSI mailboxes / protocols ──────►  SECONDARY core │
   │   (master model)                                  (secondary model)    │
   │   - comms, supervision                            - real-time PWM loop  │
   │   - high-level control                            - high-speed ADC      │
   └────────────────────────────────────────────────────────────┘

• Main (master) core: the device’s primary core — typically handles communication, supervision, and higher-level control.
• Secondary (slave) core: typically runs the time-critical inner loop (e.g. the PWM current loop and high-speed ADC sampling).
• The two cores share data through the MSI — hardware mailboxes with protocol synchronisation, no CPU polling and no copy through main RAM.

Each core is programmed from its own Simulink model. The Main project links the Secondary core’s compiled image so a single build produces one device firmware.

The two blocks

Naming convention

The secondary device part number carries an S1 suffix:

Both models target the same physical device — the suffix selects which core the model compiles for.

End-to-end workflow

1. Create the Secondary model

1. New model, drop a Microchip Master and set its target to the …S1 secondary part (e.g. dsPIC33CH512MP508S1).
2. Build the secondary algorithm (the time-critical loop — PWM, ADC, control).
3. Add an MSI block to receive references from the Main core and send measurements back.
4. Generate code → this produces the secondary core image (.s file).

2. Create the Main model

1. New model, Microchip Master set to the Main part (e.g. dsPIC33CH512MP508, no suffix).
2. Build the supervisory / comms algorithm.
3. Add an MSI block — the mirror of the secondary’s, exchanging the same data items in the opposite direction.
4. Add a SECONDARY CORE block and point it at the secondary core’s .s image from step 1 (absolute or relative path).

3. Build & deploy

Build the Main model with Build, Deploy & Start. The build links the secondary image (via the SECONDARY CORE block, which sets the model’s SlaveModelReference) so a single programming operation flashes both cores.

MSI data exchange

The MSI block moves named data items between the cores:

• Up to 16 mailboxes (16 words each), allocated automatically.
• Up to 8 protocol channels (A–H) for synchronisation / event signalling.
• Up to 32 data items per block, mixed data types.
• Bidirectional and zero-copy (shared mailbox memory).

Define matching data items on the MSI block in both models — the Main MSI sends what the Secondary MSI receives, and vice-versa.

Pin ownership rule

Output pins must be driven by exactly one core. Input pins may be read by both cores simultaneously.

When allocating peripherals across the two models, give each output-driving peripheral (PWM, digital out, UART Tx, …) to a single core. Use Port Info on each model to verify the pin map and catch conflicts before building.

Typical partitioning (motor control)

This keeps the time-critical inner loop on a core that is never stalled by communication or housekeeping running on the other core.

Related

• MSI block
• Secondary Core block
• Microchip Master block
• Port Info — verify per-core pin ownership
• Supported Devices